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S12

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freescale.com

MC9S12G Family

Reference Manual

and Data Sheet

MC9S12GRMV1

Rev.1.23

February 1, 2013

Summary of content (1292 pages)

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MC9S12G Family Reference Manual and Data Sheet S12 Microcontrollers MC9S12GRMV1 Rev.1.23 February 1, 2013 freescale.
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: freescale.com/ A full list of family members and options is included in the appendices. MC9S12G Family Reference Manual, Rev.1.
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The following revision history table summarizes changes contained in this document. Revision History Date Revision Level Sep, 2012 1.14 • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Sep, 2012 1.15 • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Sep, 2012 1.
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This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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MC9S12G Family Reference Manual, Rev.1.
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Chapter 1 Device Overview MC9S12G-Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Chapter 2 Port Integration Module (S12GPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Chapter 3 5V Analog Comparator (ACMPV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 Chapter 4 Reference Voltage Attenuator (RVAV1) . . . . . . . . . . . . . . . . . . . . . . . . . .263 Chapter 5 S12G Memory Map Controller (S12GMMCV1) . . . . . . . . . . . . . . . . . . . . .
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Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1191 Appendix B Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1249 Appendix C Ordering and Shipping Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .1269 Appendix D Package and Die Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1271 MC9S12G Family Reference Manual, Rev.1.
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Chapter 1 Device Overview MC9S12G-Family 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.2.1 MC9S12G-Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.2.
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1.9 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 1.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 1.10.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 1.10.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.5 2.6 PIM Ports - Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 2.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 2.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 2.5.3 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5.2 5.3 5.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 9 Security (S12XS9SECV2) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 9.1.3 Securing the Microcontroller . . . . . . . . .
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10.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 10.7.1 General Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 10.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Chapter 11 Analog-to-Digital Converter (ADC10B8CV2) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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13.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 13.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 16 Analog-to-Digital Converter (ADC12B16CV2) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 16.1.3 Block Diagram . . . . .
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18.2 18.3 18.4 18.5 18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 18.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 18.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . .
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20.2 20.3 20.4 20.5 20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .
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21.4.4 21.4.5 21.4.6 21.4.7 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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23.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 23.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 23.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 23.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . .
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25.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 25.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 25.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 25.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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27.2 27.3 27.4 27.5 27.6 27.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 27.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 External Signal Description . . . . . . . . . . . . . . . . .
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28.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1032 28.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1033 28.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1) 29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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30.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114 30.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1119 30.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120 30.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 30.4.
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A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 A.14 A.15 A.16 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 A.1.7 Operating Conditions . . . . . . . . . . . . . . . .
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D.3 D.4 D.5 D.6 D.7 48 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 48 QFN Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 32 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 20 TSSOP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MC9S12G Family Reference Manual, Rev.1.
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Chapter 1 Device Overview MC9S12G-Family Revision History Version Number Revision Date Rev 0.25 18-Feb-2011 • • • • • • Added Section 1.14, “Autonomous Clock (ACLK) Configuration” Corrected Figure 1-15 Corrected Figure 1-10 Corrected Figure 1-16 Corrected Figure 1-12 Typos and formatting Rev 0.26 21-Feb-2011 • • • • Updated Table 1-1(added temperatur sensor feature) Updated Section 1.3.14, “Analog-to-Digital Converter Module (ADC)” Updated Table 1-38 Typos and formatting Rev 0.
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Device Overview MC9S12G-Family communication. Typical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.
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Device Overview MC9S12G-Family Feature S12GN16 S12GNA16 S12GN32 S12GNA32 S12GN48 S12G48 S12GA48 S12G64 S12GA64 S12G96 S12GA96 S12G128 S12GA128 S12G192 S12GA192 S12G240 S12GA240 Table 1-1.
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Device Overview MC9S12G-Family Table 1-2. Maximum Peripheral Availability per Package Peripheral 20 TSSOP 32 LQFP 48 LQFP, 48 QFN 64 LQFP 100 LQFP KGD (Die) 8-Bit PWM Channels 4=0…3 6=0…5 8=0…7 8=0…7 8=0…7 8=0…7 ADC channels 6=0…5 8=0…7 12 = 0 … 11 16 = 0 … 15 16 = 0 … 15 16 = 0 … 15 DAC0 — — Yes Yes Yes Yes DAC1 — — Yes Yes Yes Yes ACMP Yes Yes Yes Yes — — Total GPIO 14 26 40 54 86 86 1.2.
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Device Overview MC9S12G-Family 1.3.1 S12 16-Bit Central Processor Unit (CPU) S12 CPU is a high-speed 16-bit processing unit: • Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution • Includes many single-byte instructions. This allows much more efficient use of ROM space.
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Device Overview MC9S12G-Family • • • • • • • 1.3.5 • 1.3.6 • 1.3.7 • Interrupt flag register for pin interrupts on ports P, J and AD Control register to configure IRQ pin operation Routing register to support programmable signal redirection in 20 TSSOP only Routing register to support programmable signal redirection in 100 LQFP package only Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages.
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Device Overview MC9S12G-Family 1.3.8 • • • • • • • System Integrity Support Power-on reset (POR) System reset generation Illegal address detection with reset Low-voltage detection with interrupt or reset Real time interrupt (RTI) Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection — Initialized out of reset using option bits located in flash memory Clock monitor supervising the correct function of the oscillator 1.3.
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Device Overview MC9S12G-Family • • Bus-off recovery by software intervention or automatically 16-bit time stamp of transmitted/received messages 1.3.12 • • • • • • • • • Up to three SCI modules Full-duplex or single-wire operation Standard mark/space non-return-to-zero (NRZ) format Selectable IrDA 1.
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Device Overview MC9S12G-Family 1.3.15 • Attenuation of ADC reference voltage with low long-term drift 1.3.16 • • • • Background Debug (BDM) Non-intrusive memory access commands Supports in-circuit programming of on-chip nonvolatile memory 1.3.20 • • On-Chip Voltage Regulator (VREG) Linear voltage regulator with bandgap reference Low-voltage detect (LVD) with low-voltage interrupt (LVI) Power-on reset (POR) circuit Low-voltage reset (LVR) 1.3.
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Device Overview MC9S12G-Family • 1.4 Four stage state sequencer Key Performance Parameters The key performance parameters of S12G devices feature: • Continuous Operating voltage of 3.15 V to 5.5 V • Operating temperature (TA) of –40˚C to 125˚C • Junction temperature (TJ) of up to 150˚C • Bus frequency (fBus) of dc to 25 MHz • Packaging: — 100-pin LQFP, 0.5 mm pitch, 14 mm x 14 mm outline — 64-pin LQFP, 0.5 mm pitch, 10 mm x 10 mm outline — 48-pin LQFP, 0.5 mm pitch, 7 mm x 7 mm outline — 48-pin QFN, 0.
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TIM 16-bit 6 … 8 channel Timer CPU12-V1 PE1 Low Power Pierce XTAL Oscillator RESET PD[7:0] Interrupt Module PTB 3-5V IO Supply VDDX1/VSSX1 VDDX2/VSSX2 VDDX3/VSSX3 DACU DAC1 AMPM Digital-Analog AMP Converter AMPP PTC PC[7:0] Internal RC Oscillator Reset Generation and Test Entry PWM 8-bit 6 … 8 channel Pulse Width Modulator PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RXCAN CAN TXCAN msCAN 2.
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Device Overview MC9S12G-Family Address Size (Bytes) Module 0x000A–0x000B MMC (Memory Map Control) 2 0x000C–0x000D PIM (Port Integration Module) 2 0x000E–0x000F Reserved 2 0x0010–0x0017 MMC (Memory Map Control) 8 0x0018–0x0019 Reserved 2 0x001A–0x001B Device ID register 2 0x001C–0x001F PIM (Port Integration Module) 4 0x0020–0x002F DBG (Debug Module) 16 0x0030–0x0033 Reserved 4 0x0034–0x003F CPMU (Clock and Power Management) 12 0x0040–0x006F TIM (Timer Module <= 8 channels)
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Device Overview MC9S12G-Family Address 1 2 3 4 5 6 7 8 Size (Bytes) Module 0x03C8–0x03CF DAC1 (Digital to Analog Converter)8 8 0x03D0–0x03FF Reserved 48 The SCI1 is not available on the S12GN8, S12GN16, S12GN32, and S12GN32 devices The SCI2 is not available on the S12GN8, S12GN16, S12GN32, S12GN32, S12G48, and S12G64 devices The SPI1 is not available on the S12GN8, S12GN16, S12GN24, and S12GN32 devices The SPI2 is not available on the S12GN8, S12GN16, S12GN32, S12GN32, S12G48, and S12G64 devices
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Device Overview MC9S12G-Family Table 1-4.
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Device Overview MC9S12G-Family Local CPU and BDM Memory Map Global Memory Map Register Space Register Space EEPROM EEPROM Flash Space Page 0xC Unimplemented RAM RAM 0x0000 0x0400 0x4000 NVMRES=0 Flash Space Page 0xD NVMRES=1 0x0_0000 0x0_0400 0x0_4000 Internal Flash NVM Space Resources Page 0x1 0x0_8000 0x8000 Paging Window Flash Space Page 0x2 0x3_0000 0xC000 Flash Space Flash Space Page 0xF Page 0xC 0x3_4000 0xFFFF Flash Space Page 0xD 0x3_8000 Flash Space Page 0xE 0x3_C00
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Device Overview MC9S12G-Family 1.6.1 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID number and Mask Set number. Table 1-5.
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Device Overview MC9S12G-Family 1.7.1 Pin Assignment Overview Table 1-6 provides a summary of which ports are available for each package option. Table 1-6.
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Device Overview MC9S12G-Family NOTE The TEST pin must be tied to ground in all applications. 1.7.2.3 BKGD / MODC — Background Debug and Mode Pin The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has an internal pull-up device. 1.7.2.
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Device Overview MC9S12G-Family 1.7.2.11 PJ[7:0] / KWJ[7:0] — Port J I/O Signals PJ[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wakeup capability (KWJ[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are enabled . 1.7.2.12 PM[3:0] — Port M I/O Signals PM[3:0] are general-purpose input or output signals.
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Device Overview MC9S12G-Family 1.7.2.18 1.7.2.18.1 DAC Signals DACU[1:0] Output Pins These analog pins is used for the unbuffered analog output Voltages from the DAC0 and the DAC1 resistor network output, when the according mode is selected. 1.7.2.18.2 AMP[1:0] Output Pins These analog pins are used for the buffered analog outputs Voltage from the operational amplifier outputs, when the according mode is selected. 1.7.2.18.
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Device Overview MC9S12G-Family 1.7.2.20.2 TXD[2:0] Signals Those signals are associated with the transmit functionality of the serial communication interfaces SCI2-0. 1.7.2.21 1.7.2.21.1 CAN signals RXCAN Signal This signal is associated with the receive functionality of the scalable controller area network controller (MSCAN). 1.7.2.21.2 TXCAN Signal This signal is associated with the transmit functionality of the scalable controller area network controller (MSCAN). 1.7.2.
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Device Overview MC9S12G-Family 1.7.2.25 IRQ This signal is associated with the maskable IRQ interrupt. 1.7.2.26 XIRQ This signal is associated with the non-maskable XIRQ interrupt. 1.7.2.27 ETRIG[3:0] These signals are inputs to the Analog-to-Digital Converter. Their purpose is to trigger ADC conversions. 1.7.3 Power Supply Pins MC9S12G power and ground pins are described below.
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Device Overview MC9S12G-Family 1.7.3.4 VDDA, VSSA — Power Supply Pins for DAC,ACMP, RVA, ADC and Voltage Regulator These are the power supply and ground input pins for the digital-to-analog converter, the analog comparator, the reference voltage attenuator, the analog-to-digital converter and the voltage regulator. NOTE On some packages VDDA is connected with VDDXR and the common pin is named VDDXRA. On some packages the VSSA is connected to VSSX and the common pin is named VSSXA. See section Section 1.
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Device Overview MC9S12G-Family 1.8 Device Pinouts 1.8.1 1.8.1.
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Device Overview MC9S12G-Family Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 32-Pin LQFP 32 31 30 29 28 27 26 25 PM1 PM0 PS7/API_EXTCLK/ECLK/PWM5/SS0 PS6/IOC5/SCK0 PS5/IOC4/MOSI0 PS4/PWM4/MISO0 PS1/TXD0 PS0/RXD0 1.8.1.
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Device Overview MC9S12G-Family Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 4 PE01 EXTAL — — — 5 VSS — — — 6 PE11 XTAL — 7 TEST — 8 BKGD 9 Power Supply Internal Pull Resistor CTRL Reset State — PUCR/PDPEE Down — — — — — — — PUCR/PDPEE Down — — — N.A.
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Device Overview MC9S12G-Family 1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Pinout 48-Pin LQFP/QFN 48 47 46 45 44 43 42 41 40 39 38 37 PM1 PM0 PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3 PS2 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.1.
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Device Overview MC9S12G-Family Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY-----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 1 RESET — — — — VDDX 2 VDDXR — — — — — — — 3 VSSX — — — — — — — 4 1 PE0 EXTAL — — — VDDX PUCR/PDPEE Down 5 VSS — — — — — — — 6 PE11 XTAL — — — VDDX PUCR/PDPEE Down 7 TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family 1.8.2 Pinout 48-Pin LQFP/QFN 48 47 46 45 44 43 42 41 40 39 38 37 PM1 PM0 PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3 PS2 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.2.
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Device Overview MC9S12G-Family Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 2 VDDXR — — — — 3 VSSX — — — 4 PE01 EXTAL — 5 VSS — 6 PE1 1 7 Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — VDDX PUCR/PDPEE Down — — — — — — XTAL — — — VDDX PUCR/PDPEE Down TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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32 31 30 29 28 27 26 25 PM1/TXD1 PM0/RXD1 PS7/API_EXTCLK/ECLK/PWM5/SS0 PS6/IOC5/SCK0 PS5/IOC4/MOSI0 PS4/PWM4/MISO0 PS1/TXD0 PS0/RXD0 Device Overview MC9S12G-Family 1 2 3 4 5 6 7 8 S12GN48 32-Pin LQFP 24 23 22 21 20 19 18 17 PAD7/KWAD7/AN7/ACMPM PAD6/KWAD6/AN6/ACMPP PAD5/KWAD5/AN5/ACMPO PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/
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Device Overview MC9S12G-Family Table 1-12. 32-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 5 VSS — — — — 6 PE11 XTAL — — 7 TEST — — 8 BKGD MODC 9 PP0 10 Power Supply Internal Pull Resistor CTRL Reset State — — — — — PUCR/PDPEE Down — — N.A.
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Device Overview MC9S12G-Family Pinout 48-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 PM1 PM0 PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.3.
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Device Overview MC9S12G-Family Table 1-13. 48-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 3 VSSX — — — — 4 PE01 EXTAL — — 5 VSS — — 6 PE11 XTAL 7 TEST 8 Power Supply Internal Pull Resistor CTRL Reset State — — — — VDDX PUCR/PDPEE Down — — — — — — — — VDDX PUCR/PDPEE Down — — — — N.A.
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Device Overview MC9S12G-Family Table 1-13. 48-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 64-Pin LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PJ7/KWJ7 PM3 PM2 PM1 PM0 PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH 1.8.3.
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Device Overview MC9S12G-Family Table 1-14. 64-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-14. 64-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-14. 64-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family 1.8.4 S12G48 and S12G64 Pinout 32-Pin LQFP 32 31 30 29 28 27 26 25 PM1/TXD1/TXCAN PM0/RXD1/RXCAN PS7/API_EXTCLK/ECLK/PWM5/SS0 PS6/IOC5/SCK0 PS5/IOC4/MOSI0 PS4/PWM4/MISO0 PS1/TXD0 PS0/RXD0 1.8.4.
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Device Overview MC9S12G-Family Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 2 VDDXRA VRH — — — 3 VSSXA — — — 4 PE01 EXTAL — 5 VSS — 6 1 PE1 7 Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — — PUCR/PDPEE Down — — — — — — XTAL — — — — PUCR/PDPEE Down TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 31 PM0 RXD1 RXCAN — — 32 PM1 TXD1 TXCAN — — Internal Pull Resistor Power Supply CTRL Reset State VDDX PERM/PPSM Disabled VDDX PERM/PPSM Disabled The regular I/O characteristics (see Section A.
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Device Overview MC9S12G-Family Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY-----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 1 RESET — — — — VDDX 2 VDDXR — — — — — — — 3 VSSX — — — — — — — 4 1 PE0 EXTAL — — — VDDX PUCR/PDPEE Down 5 VSS — — — — — — — 6 PE11 XTAL — — — VDDX PUCR/PDPEE Down 7 TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 64-Pin LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PJ7/KWJ7 PM3 PM2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH 1.8.4.
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Device Overview MC9S12G-Family Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family 1.8.5 Pinout 48-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.5.
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Device Overview MC9S12G-Family Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 2 VDDXR — — — — 3 VSSX — — — 4 PE01 EXTAL — 5 VSS — 6 PE1 1 7 Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — VDDX PUCR/PDPEE Down — — — — — — XTAL — — — VDDX PUCR/PDPEE Down TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 64-Pin LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PJ7/KWJ7 PM3 PM2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH 1.8.5.
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Device Overview MC9S12G-Family Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family 1.8.6 Pinout 48-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 PM1/TXD2/TXCAN PM0/RXD2/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.6.
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Device Overview MC9S12G-Family Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 2 VDDXR — — — — 3 VSSX — — — 4 PE01 EXTAL — 5 VSS — 6 PE1 1 7 Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — VDDX PUCR/PDPEE Down — — — — — — XTAL — — — VDDX PUCR/PDPEE Down TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 64-Pin LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH 1.8.6.
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Device Overview MC9S12G-Family Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 100-Pin LQFP S12G96 S12G128 100-Pin LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VRH PC7 PC6 PC5 PC4 PAD15/KWAD15/ PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/A
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Device Overview MC9S12G-Family Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family 1.8.7 Pinout 48-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 PM1/TXD2/TXCAN PM0/RXD2/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.7.
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Device Overview MC9S12G-Family Table 1-23. 48-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 2 VDDXR — — — — 3 VSSX — — — 4 PE01 EXTAL — 5 VSS — 6 PE1 1 7 Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — VDDX PUCR/PDPEE Down — — — — — — XTAL — — — VDDX PUCR/PDPEE Down TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-23. 48-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 64-Pin LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH 1.8.7.
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Device Overview MC9S12G-Family Table 1-24. 64-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-24. 64-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-24. 64-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 100-Pin LQFP S12GA96 S12GA128 100-Pin LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VRH PC7 PC6 PC5 PC4 PAD15/KWAD15/ PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9
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Device Overview MC9S12G-Family Table 1-25. 100-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-25. 100-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-25. 100-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-25. 100-Pin LQFP Pinout for S12GA96 and S12GA128 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family 1.8.8 Pinout 48-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 PM1/TXD2/TXCAN PM0/RXD2/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.8.
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Device Overview MC9S12G-Family Table 1-26. 48-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 2 VDDXR — — — — 3 VSSX — — — 4 PE01 EXTAL — 5 VSS — 6 PE1 1 7 Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — VDDX PUCR/PDPEE Down — — — — — — XTAL — — — VDDX PUCR/PDPEE Down TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-26. 48-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 64-Pin LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH 1.8.8.
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Device Overview MC9S12G-Family Table 1-27. 64-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
PAGE 124
Device Overview MC9S12G-Family Table 1-27. 64-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
PAGE 125
Device Overview MC9S12G-Family Table 1-27. 64-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
PAGE 126
Device Overview MC9S12G-Family Pinout 100-Pin LQFP S12G192 S12G240 100-Pin LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VRH PC7 PC6 PC5 PC4 PAD15/KWAD15/AN15 PAD7/KWAD7/AN7 PAD14/KWAD14/AN14 PAD6/KWAD6/AN6 PAD13/KWAD13/AN13 PAD5/KWAD5/AN5 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KW
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Device Overview MC9S12G-Family Table 1-28. 100-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
PAGE 128
Device Overview MC9S12G-Family Table 1-28. 100-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
PAGE 129
Device Overview MC9S12G-Family Table 1-28. 100-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
PAGE 130
Device Overview MC9S12G-Family Table 1-28. 100-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family 1.8.9 Pinout 48-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 PM1/TXD2/TXCAN PM0/RXD2/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH 1.8.9.
PAGE 132
Device Overview MC9S12G-Family Table 1-29. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 2 VDDXR — — — — 3 VSSX — — — 4 PE01 EXTAL — 5 VSS — 6 PE1 1 7 Power Supply Internal Pull Resistor CTRL Reset State — — — — — — — — — VDDX PUCR/PDPEE Down — — — — — — XTAL — — — VDDX PUCR/PDPEE Down TEST — — — — N.A.
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Device Overview MC9S12G-Family Table 1-29. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 64-Pin LQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH 1.8.9.
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Device Overview MC9S12G-Family Table 1-30. 64-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-30. 64-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Table 1-30. 64-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func.
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Device Overview MC9S12G-Family Pinout 100-Pin LQFP S12GA192 S12GA240 100-Pin LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VRH PC7/DACU1 PC6/AMPP1 PC5/AMPM1 PC4 PAD15/KWAD15/AN15/DACU0 PAD7/KWAD7/AN7 PAD14/KWAD14/AN14/AMPP0 PAD6/KWAD6/AN6 PAD13/KWAD13/AN13/AMPM0 PAD5/KWAD5/AN5 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/AM
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Device Overview MC9S12G-Family Table 1-31. 100-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-31. 100-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-31. 100-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-31. 100-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> 1 Package Pin Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family 1.8.9.4 Known Good Die Option (KGD) Table 1-32. KGD Option for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Wire Bond Die Pad Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-32. KGD Option for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Wire Bond Die Pad Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-32. KGD Option for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> Wire Bond Die Pad Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family Table 1-32. KGD Option for S12GA192 and S12GA240 Function <----lowest-----PRIORITY-----highest----> 1 Wire Bond Die Pad Pin 2nd Func. 3rd Func. 4th Func.
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Device Overview MC9S12G-Family The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-33). The MODC bit in the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET. Table 1-33. Chip Modes Chip Modes 1.10.1.
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Device Overview MC9S12G-Family Table 1-34. Reset Sources and Vector Locations 1.12.
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Device Overview MC9S12G-Family Table 1-35.
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Device Overview MC9S12G-Family 1.12.3 Effects of Reset When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On each reset, the Flash module executes a reset sequence to load Flash configuration registers. 1.12.3.1 Flash Configuration Reset Sequence Phase On each reset, the Flash module holds CPU activity while loading Flash module registers from the Flash memory.
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Device Overview MC9S12G-Family Table 1-37. Initial WCOP Configuration 1.14 NV[3] in FOPT Register WCOP in CPMUCOP Register 1 0 0 1 Autonomous Clock (ACLK) Configuration The autonomous clock1 (ACLK) is not factory trimmed. The reset value of the autonomous clock trimming register2 (CPMUACLKTR) is 0xFC. 1.15 ADC External Trigger Input Connection The ADC module includes external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3.
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Device Overview MC9S12G-Family 1.17 ADC Result Reference MCUs of the S12G-Family are able to measure the internal reference voltage VDDF (see Table 1-38). VDDF is a constant voltage with a narrow distribution over temperature and external voltage supply (see Table A-43). A 12-bit left justified1 ADC conversion result of VDDF is provided at address 0x0_4022/0x0_4023 in the NVM’s IFR for reference.The measurement conditions of the reference conversion are listed in Section A.
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Device Overview MC9S12G-Family The S12GA192 and the S12GA240 contain a Reference Voltage Attenuator (RVA) module. The connection of the ADC’s VRH/VRL inputs on these devices is shown in Figure 1-27. S12GN16, S12GNA16, S12GN32, S12GNA32, S12GN48, S12G48, S12GA48, S12G64, S12GA64, S12G96, S12GA96, S12G128, S12GA128, S12G192, S12G240 ADC VRH VRH VRL VSSA S12GA192, S12GA240 RVA VRH VRH ADC VRH_INT VRH VRL_INT VRL VSSA VSSA Figure 1-27. ADC VRH/VRL Signal Connection 1.
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Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.
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Chapter 2 Port Integration Module (S12GPIMV1) Revision History Rev. No. (Item No.) Date (Submitted By) Sections Affected V01.01 01 Dec 2010 Table 2-4 Table 2-5 Table 2-8 Table 2-16 Table 2-17 V01.02 30 Aug 2011 2.4.3.40/2-23 2 2.4.3.48/2-23 8 2.4.3.63/2-24 7 2.4.3.64/2-24 8 V01.03 15 Mar 2012 Table 2-2./2-1 • Added GA and GNA derivatives 58 Table 2-4./2-1 62 2.
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Port Integration Module (S12GPIMV1) Term Definition Port 2.1.2 Group of general-purpose I/O pins sharing peripheral signals Overview The PIM establishes the interface between the peripheral modules and the I/O pins. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. The family devices share same sets of package options (refer to device overview section) determining the availability of pins and the related PIM memory maps.
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Port Integration Module (S12GPIMV1) • • Control register for free-running clock outputs A standard port pin has the following minimum features: • Input/output selection • 3.15 V - 5 V digital and analog input • Input with selectable pullup or pulldown device Optional features supported on dedicated pins: • Open drain for wired-or connections • Key-wakeup feature: External pin interrupt with glitch filtering, which can also be used for wakeup from stop mode. 2.1.4 Block Diagram Figure 2-1.
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Port Integration Module (S12GPIMV1) Table 2-3. Port Pin Availability (in largest package) per Device Device Group Port 2.2.1 G1 (100 pin) G2 (64 pin) G3 (48 pin) C 7-0 - - D 7-0 - - E 1-0 1-0 1-0 T 7-0 7-0 5-0 S 7-0 7-0 7-0 M 3-0 3-0 1-0 P 7-0 7-0 5-0 J 7-0 7-0 3-0 AD 15-0 15-0 11-0 Package Code The availability of pins and the related peripheral signals are determined by a package code (Section 2.4.3.33, “Package Code Register (PKGCR)”).
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Port Integration Module (S12GPIMV1) index in PTI, DDR, PER, PPS, and where applicable in PIE, PIF or WOM (see Section 2.4, “PIM Ports Memory Map and Register Definition”). For example pin PAD15: Signal [PT0AD7] is bit 7 of register PT0AD; other related register bits of this pin are PTI0AD7, DDR0AD7, PER0AD7, PPS0AD7, PIE0AD7 and PIF0AD7.
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Port Integration Module (S12GPIMV1) 2.3 PIM Routing - Functional description Table 2-4.
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Port Integration Module (S12GPIMV1) Table 2-4.
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Port Integration Module (S12GPIMV1) Table 2-4.
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Port Integration Module (S12GPIMV1) Table 2-4.
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Port Integration Module (S12GPIMV1) Table 2-4.
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Port Integration Module (S12GPIMV1) Table 2-4.
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Port Integration Module (S12GPIMV1) Table 2-4.
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Port Integration Module (S12GPIMV1) Table 2-4. Signals and Priorities 100 AD PAD7 PAD6 PAD5 ACMPM 64 48 AN7 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ACMPP AN6 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ GN16 GN32 Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin I/O Description I ACMP inverting input (-) I ADC analog I ACMP non-inv.
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Port Integration Module (S12GPIMV1) This section describes the signals available on each pin. Although trying to enable multiple signals on a shared pin is not a proper use case in most applications, the resulting pin function will be determined by a predefined priority scheme as defined in 2.2.2 and 2.2.3. Only enabled signals arbitrate for the pin and the highest priority defines its data direction and output value if used as output.
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Port Integration Module (S12GPIMV1) 2.3.1 Pin BKGD Table 2-5. Pin BKGD BKGD 2.3.2 • The BKGD pin is associated with the BDM module in all packages. During reset, the BKGD pin is used as MODC input. Pins PA7-0 Table 2-6. Port A Pins PA7-0 PA7-PA0 2.3.3 • These pins feature general-purpose I/O functionality only. Pins PB7-0 Table 2-7. Port B Pins PB7-0 PB7-PB6 • These pins feature general-purpose I/O functionality only.
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Port Integration Module (S12GPIMV1) • When routing of ADC channels to PC4-PC0 is selected (PRR1[PRR1AN]=1) the related bit in the ADC Digital Input Enable Register (ATDDIEN) must be set to 1 to activate the digital input function on those pins not used as ADC inputs. If the external trigger source is one of the ADC channels, the digital input buffer of this channel is automatically enabled. Table 2-8.
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Port Integration Module (S12GPIMV1) 2.3.5 Pins PD7-0 Table 2-9. Port D Pins PD7-0 PD7-PD0 2.3.6 • These pins feature general-purpose I/O functionality only. Pins PE1-0 Table 2-10. Port E Pins PE1-0 PE1 • If the CPMU OSC function is active this pin is used as XTAL signal and the pulldown device is disabled. • 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration.
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Port Integration Module (S12GPIMV1) Table 2-11. Port T Pins PT7-0 (continued) PT4 • 48/64/100 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. • Signal priority: 48/64/100 LQFP: IOC4 > GPO PT3-PT2 • Except 20 TSSOP: The TIM channels 3 and 2 signal are mapped to these pins when used with the timer function.
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Port Integration Module (S12GPIMV1) 2.3.8 Pins PS7-0 Table 2-12. Port S Pins PS7-0 PS7 • The SPI0 SS signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI0 the I/O state is forced to be input or output. • 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration.
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Port Integration Module (S12GPIMV1) Table 2-12. Port S Pins PS7-0 (continued) PS4 • The SPI0 MISO signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI0 the I/O state is forced to be input or output. • 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled and routed here the I/O state will be forced to input.
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Port Integration Module (S12GPIMV1) 2.3.9 Pins PM3-0 Table 2-13. Port M Pins PM3-0 PM3 • 64/100 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2 TXD signal is enabled the I/O state will depend on the SCI2 configuration. • Signal priority: 64/100 LQFP: TXD2 > GPO PM2 • 64/100 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. If the SCI2 RXD signal is enabled the I/O state will be forced to be input.
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Port Integration Module (S12GPIMV1) Table 2-14. Port P Pins PP7-0 (continued) PP3-PP2 • Except 20 TSSOP: The PWM channels 3 and 2 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state to be an output. • Except 20 TSSOP: The ADC ETRIG 3 and 2 signal are mapped to these pins when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”.
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Port Integration Module (S12GPIMV1) 2.3.11 Pins PJ7-0 Table 2-15. Port J Pins PJ7-0 PJ7 • 64/100 LQFP: The SPI2 SS signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI2 the I/O state is forced to be input or output. • 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode. • Signal priority: 64/100 LQFP: SS2 > GPO PJ6 • 64/100 LQFP: The SPI2 SCK signal is mapped to this pin when used with the SPI function.
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Port Integration Module (S12GPIMV1) Table 2-15. Port J Pins PJ7-0 (continued) PJ1 • Except 20 TSSOP and 32 LQFP: The SPI1 MOSI signal is mapped to this pin when used with the SPI function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or output. • 48 LQFP: The TIM channel 6 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output.
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Port Integration Module (S12GPIMV1) Table 2-16. Port AD Pins AD15-8 PAD15 • 64/100 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled. • 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN15 and the related digital trigger input are mapped to this pin.
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Port Integration Module (S12GPIMV1) Table 2-16. Port AD Pins AD15-8 PAD11 • 64/100 LQFP: The buffered analog output signal AMP0 of the DAC0 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational amplifier” or “operational amplifier only” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled.
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Port Integration Module (S12GPIMV1) Table 2-16. Port AD Pins AD15-8 PAD9 • 48/64 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output. • 48/64/100 LQFP: The ADC analog input channel signal AN9 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-180 for input buffer control.
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Port Integration Module (S12GPIMV1) Table 2-17. Port AD Pins AD7-0 (continued) PAD5 • 32 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output. • 20 TSSOP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-180 for input buffer control.
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Port Integration Module (S12GPIMV1) Table 2-17. Port AD Pins AD7-0 (continued) PAD3 • 20 TSSOP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output. • The ADC analog input channel signal AN3 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-180 for input buffer control.
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Port Integration Module (S12GPIMV1) 2.4 PIM Ports - Memory Map and Register Definition This section provides a detailed description of all PIM registers. 2.4.1 Memory Map Table 2-18 shows the memory maps of all groups (for definitions see Table 2-2). Addresses 0x0000 to 0x0007 are only implemented in group G1 otherwise reserved. Table 2-18.
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Port Integration Module (S12GPIMV1) Table 2-18. Block Memory Map (0x0000-0x027F) (continued) Port Global Address T 0x0240 S M P Register Access Reset Value Section/Page PTT—Port T Data Register R/W 0x00 2.4.3.15/2-215 0x0241 PTIT—Port T Input Register R 3 2.4.3.16/2-215 0x0242 DDRT—Port T Data Direction Register R/W 0x00 2.4.3.17/2-216 0x0243 Reserved R 0x00 0x0244 PERT—Port T Pull Device Enable Register R/W 0x00 2.4.3.
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Port Integration Module (S12GPIMV1) Table 2-18. Block Memory Map (0x0000-0x027F) (continued) Port Global Address 0x0260 Register Reserved for ACMP available in group G2 and G3 0x0261 J AD Access Reset Value Section/Page R(/W) 0x00 (ACMP) R(/W) 0x00 (ACMP) R 0x00 0x0262 : 0x0266 Reserved 0x0268 PTJ—Port J Data Register R/W 0x00 2.4.3.42/2-234 0x0269 PTIJ—Port J Input Register R 3 2.4.3.43/2-235 0x026A DDRJ—Port J Data Direction Register R/W 0x00 2.4.3.
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Port Integration Module (S12GPIMV1) 5 6 Preset by factory. Routing register only available on G(A)240 and G(A)192 only. Takes only effect if the PKGCR is set to 100 LQFP. 2.4.2 Register Map The following tables show the individual register maps of groups G1 (Table 2-19), G2 (Table 2-20) and G3 (Table 2-21). NOTE To maintain SW compatibility write data to unimplemented register bits must be zero. 2.4.2.1 Block Register Map (G1) Table 2-19.
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Port Integration Module (S12GPIMV1) Table 2-19.
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Port Integration Module (S12GPIMV1) Table 2-19.
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Port Integration Module (S12GPIMV1) Table 2-19.
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Port Integration Module (S12GPIMV1) Table 2-19.
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Port Integration Module (S12GPIMV1) Table 2-19.
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Port Integration Module (S12GPIMV1) Table 2-20.
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Port Integration Module (S12GPIMV1) Table 2-20.
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Port Integration Module (S12GPIMV1) Table 2-20.
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Port Integration Module (S12GPIMV1) Table 2-20.
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Port Integration Module (S12GPIMV1) Table 2-20.
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Port Integration Module (S12GPIMV1) Table 2-21.
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Port Integration Module (S12GPIMV1) Table 2-21.
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Port Integration Module (S12GPIMV1) Table 2-21.
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Port Integration Module (S12GPIMV1) Table 2-21.
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Port Integration Module (S12GPIMV1) Table 2-21. Block Register Map (G3) (continued) Global Address Register Name 0x027C PIE0AD R Bit 7 6 5 4 0 0 0 0 PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 0 0 0 0 PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 W 0x027D PIE1AD R W 0x027E PIF0AD R W 0x027F PIF1AD R W 3 2 1 Bit 0 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 = Unimplemented or Reserved 2.4.
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Port Integration Module (S12GPIMV1) 2.4.3.1 Port A Data Register (PORTA) Access: User read/write1 Address 0x0000 (G1) 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 0 0 0 0 0 0 0 0 R W Reset Address 0x0000 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-2. Port A Data Register (PORTA) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-22.
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Port Integration Module (S12GPIMV1) 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-23. PORTB Register Field Descriptions Field Description 7-0 PB Port B general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin.
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Port Integration Module (S12GPIMV1) 2.4.3.4 Port B Data Direction Register (DDRB) Access: User read/write1 Address 0x0003 (G1) 7 6 5 4 3 2 1 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 R W Reset Address 0x0003 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-5. Port B Data Direction Register (DDRB) 1 Read: Anytime Write: Anytime Table 2-25.
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Port Integration Module (S12GPIMV1) Table 2-26. PORTC Register Field Descriptions Field Description 7-0 PC Port C general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.7 Port C Data Direction Register (DDRC) Access: User read/write1 Address 0x0006 (G1) 7 6 5 4 3 2 1 0 DDRC7 DDRC6 DDRC5 DDRA4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 R W Reset Address 0x0006 (G2, G3) R Access: User read only 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 2-8. Port C Data Direction Register (DDRC) 1 Read: Anytime Write: Anytime Table 2-28.
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Port Integration Module (S12GPIMV1) Table 2-29. DDRD Register Field Descriptions Field 7-0 DDRD Description Port D Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.9 Port E Data Register (PORTE) Access: User read/write1 Address 0x0008 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 PE1 PE0 0 0 W Reset 0 0 0 0 0 0 Figure 2-10. Port E Data Register (PORTE) 1 Read: Anytime.
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Port Integration Module (S12GPIMV1) Table 2-31. DDRE Register Field Descriptions Field 1-0 DDRE Description Port E Data Direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.
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Port Integration Module (S12GPIMV1) Table 2-32. PUCR Register Field Descriptions (continued) Field 2 PUPCE Description Port C Pullup Enable—Enable pullup devices on all port input pins This bit configures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect.
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Port Integration Module (S12GPIMV1) 2.4.3.12 ECLK Control Register (ECLKCTL) Access: User read/write1 Address 0x001C 7 6 5 4 3 2 1 0 NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 1 1 0 0 0 0 0 0 R W Reset: Figure 2-13. ECLK Control Register (ECLKCTL) 1 Read: Anytime Write: Anytime Table 2-33. ECLKCTL Register Field Descriptions Field Description 7 NECLK No ECLK—Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin.
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Port Integration Module (S12GPIMV1) 1 Read: Anytime Write: IRQE: Once in normal mode, anytime in special mode IRQEN: Anytime Table 2-34. IRQCR Register Field Descriptions Field 7 IRQE Description IRQ select edge sensitive only— 1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
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Port Integration Module (S12GPIMV1) 2.4.3.15 Port T Data Register (PTT) Access: User read/write1 Address 0x0240 (G1, G2) 7 6 5 4 3 2 1 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x0240 (G3) R 7 6 0 0 5 4 3 2 1 0 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 0 0 0 0 0 0 W Reset 0 0 Figure 2-16. Port T Data Register (PTT) 1 Read: Anytime. The data source is depending on the data direction value.
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Port Integration Module (S12GPIMV1) Table 2-36. PTIT Register Field Descriptions Field Description 7-0 PTIT Port T input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.18 Port T Pull Device Enable Register (PERT) Access: User read/write1 Address 0x0244 (G1, G2) 7 6 5 4 3 2 1 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x0244 (G3) R 7 6 0 0 5 4 3 2 1 0 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 0 0 0 0 0 0 W Reset 0 0 Figure 2-19. Port T Pull Device Enable Register (PERT) 1 Read: Anytime Write: Anytime Table 2-38.
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Port Integration Module (S12GPIMV1) 2.4.3.19 Port T Polarity Select Register (PPST) Access: User read/write1 Address 0x0245 (G1, G2) 7 6 5 4 3 2 1 0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x0245 (G3) R 7 6 0 0 5 4 3 2 1 0 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 W Reset 0 0 Figure 2-20. Port T Polarity Select Register (PPST) 1 Read: Anytime Write: Anytime Table 2-39.
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Port Integration Module (S12GPIMV1) Table 2-40. PTS Register Field Descriptions Field 7-0 PTS 2.4.3.21 Description Port S general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read.
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Port Integration Module (S12GPIMV1) Table 2-42. DDRS Register Field Descriptions Field 7-0 DDRS Description Port S data direction— This bit determines whether the associated pin is a general-purpose input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.
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Port Integration Module (S12GPIMV1) Table 2-44. PPSS Register Field Descriptions Field 7-0 PPSS Description Port S pull device select—Configure pull device polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. 1 Pulldown device selected 0 Pullup device selected 2.4.3.
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Port Integration Module (S12GPIMV1) Table 2-46. PRR0 Register Field Descriptions Field Description 7 PRR0P3 Pin Routing Register PWM3 —Select alternative routing of PWM3 output, ETRIG3 input This bit programs the routing of the PWM3 channel and the ETRIG3 input to a different external pin in 20 TSSOP. See Table 2-47 for more details.
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Port Integration Module (S12GPIMV1) Table 2-50. IOC2 Routing Options PRR0T21 PRR0T20 IOC2 Associated Pin 0 0 PS5 - IOC2 0 1 PE0 - IOC2 1 0 PAD4 - IOC2 1 1 Reserved Table 2-51. SCI0 Routing Options 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.28 Port M Input Register (PTIM) Access: User read only1 Address 0x0251 (G1, G2) R 7 6 5 4 3 2 1 0 0 0 0 0 PTIM3 PTIM2 PTIM1 PTIM0 0 0 0 0 0 0 0 0 W Reset Access: User read only1 Address 0x0251 (G3) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PTIM1 PTIM0 0 0 0 0 0 0 0 0 W Reset Figure 2-29. Port M Input Register (PTIM) 1 Read: Anytime Write:Never Table 2-53.
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Port Integration Module (S12GPIMV1) Table 2-54. DDRM Register Field Descriptions Field 3-0 DDRM Description Port M data direction— This bit determines whether the associated pin is a general-purpose input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.31 Port M Polarity Select Register (PPSM) Access: User read/write1 Address 0x0255 (G1, G2) R 7 6 5 4 0 0 0 0 3 2 1 0 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 W Reset 0 0 0 0 Access: User read/write1 Address 0x0255 (G3) R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 PPSM1 PPSM0 0 0 W Reset 0 0 0 0 0 0 Figure 2-32. Port M Polarity Select Register (PPSM) 1 Read: Anytime Write: Anytime Table 2-56.
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Port Integration Module (S12GPIMV1) Table 2-57. WOMM Register Field Descriptions Field Description 3-0 WOMM Port M wired-or mode—Enable open-drain functionality on output pin This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no influence on pins used as input. 1 Output buffer operates as open-drain output.
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Port Integration Module (S12GPIMV1) Table 2-59. API_EXTCLK Routing Options APICLKS7 API_EXTCLK Associated Pin 0 PB1 (100 LQFP) PP0 (64/48/32 LQFP) N.C. (20TSSOP) 1 PS7 Table 2-60. Package Options 1 2.4.3.34 PKGCR2 PKGCR1 PKGCR0 Selected Package 1 1 1 Reserved1 1 1 0 100 LQFP 1 0 1 Reserved 1 0 0 64 LQFP 0 1 1 48 LQFP 0 1 0 Reserved 0 0 1 32 LQFP 0 0 0 20 TSSOP Reading this value indicates an illegal code write or uninitialized factory programming.
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Port Integration Module (S12GPIMV1) Table 2-61. PTP Register Field Descriptions Field 7-0 PTP 2.4.3.35 Description Port P general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read.
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Port Integration Module (S12GPIMV1) 2.4.3.36 Port P Data Direction Register (DDRP) Access: User read/write1 Address 0x025A (G1, G2) 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x025A (G3) R 7 6 0 0 5 4 3 2 1 0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 W Reset 0 0 Figure 2-37. Port P Data Direction Register (DDRP) 1 Read: Anytime Write: Anytime Table 2-63.
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Port Integration Module (S12GPIMV1) Table 2-64. PERP Register Field Descriptions Field Description 7-0 PERP Port P pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. 1 Pull device enabled 0 Pull device disabled 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.39 Port P Interrupt Enable Register (PIEP) Read: Anytime Access: User read/write1 Address 0x025E (G1, G2) 7 6 5 4 3 2 1 0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x025E (G3) R 7 6 0 0 5 4 3 2 1 0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 0 0 0 0 0 0 W Reset 0 0 Figure 2-40.
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Port Integration Module (S12GPIMV1) 1 Read: Anytime Write: Anytime, write 1 to clear Table 2-67. PIFP Register Field Descriptions Field Description 7-0 PIFP Port P interrupt flag— This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set.
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Port Integration Module (S12GPIMV1) 2.4.3.41 Reserved Registers NOTE Addresses 0x0260-0x0261 are reserved for ACMP registers in G2 and G3 only. Refer to ACMP section “ACMP Control Register (ACMPC)” and “ACMP Status Register (ACMPS)”. 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.43 Port J Input Register (PTIJ) Access: User read only1 Address 0x0269 (G1, G2) R 7 6 5 4 3 2 1 0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset Access: User read only1 Address 0x0269 (G3) R 7 6 5 4 3 2 1 0 0 0 0 0 PTIJ3 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset Figure 2-43. Port J Input Register (PTIJ) 1 Read: Anytime Write:Never Table 2-69.
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Port Integration Module (S12GPIMV1) Table 2-70. DDRJ Register Field Descriptions Field 7-0 DDRJ Description Port J data direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.46 Port J Polarity Select Register (PPSJ) Access: User read/write1 Address 0x026D (G1, G2) 7 6 5 4 3 2 1 0 PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x026D (G3) R 7 6 5 4 0 0 0 0 3 2 1 0 PPSJ3 PPSJ2 PPSJ1 PPSJ0 0 0 0 0 W Reset 0 0 0 0 Figure 2-46. Port J Polarity Select Register (PPSJ) 1 Read: Anytime Write: Anytime Table 2-72.
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Port Integration Module (S12GPIMV1) 1 Read: Anytime Write: Anytime Table 2-73. PIEJ Register Field Descriptions Field Description 7-0 PIEJ Port J interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.49 Port AD Data Register (PT0AD) Access: User read/write1 Address 0x0270 (G1, G2) 7 6 5 4 3 2 1 0 PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x0270 (G3) R 7 6 5 4 0 0 0 0 3 2 1 0 PT0AD3 PT0AD2 PT0AD1 PT0AD0 0 0 0 0 W Reset 0 0 0 0 Figure 2-49. Port AD Data Register (PT0AD) 1 Read: Anytime.
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Port Integration Module (S12GPIMV1) Table 2-76. PT1AD Register Field Descriptions Field 7-0 PT1AD 2.4.3.51 Description Port AD general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin.
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Port Integration Module (S12GPIMV1) Table 2-78. PTI1AD Register Field Descriptions Field Description 7-0 PTI1AD Port AD input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. 2.4.3.
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Port Integration Module (S12GPIMV1) Table 2-80. DDR1AD Register Field Descriptions Field 7-0 DDR1AD Description Port AD data direction— This bit determines whether the associated pin is an input or output. 1 Associated pin configured as output 0 Associated pin configured as input 2.4.3.55 Reserved Register NOTE Address 0x0276 is reserved for RVA on G(A)240 and G(A)192 only. Refer to RVA section “RVA Control Register (RVACTL)”. 2.4.3.
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Port Integration Module (S12GPIMV1) Table 2-82. AN Routing Options PRR1AN 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.58 Port AD Pull Enable Register (PER1AD) Access: User read/write1 Address 0x0279 7 6 5 4 3 2 1 0 PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 0 0 0 0 0 0 0 0 R W Reset Figure 2-57. Port AD Pullup Enable Register (PER1AD) 1 Read: Anytime Write: Anytime Table 2-84.
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Port Integration Module (S12GPIMV1) Table 2-85. PPS0AD Register Field Descriptions Field 7-0 PPS0AD Description Port AD pull device select—Configure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. 1 Pulldown device selected; rising edge selected 0 Pullup device selected; falling edge selected 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.61 Port AD Interrupt Enable Register (PIE0AD) Read: Anytime Access: User read/write1 Address 0x027C (G1, G2) 7 6 5 4 3 2 1 0 PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 0 0 0 0 0 0 0 0 R W Reset Access: User read/write1 Address 0x027C (G3) R 7 6 5 4 0 0 0 0 3 2 1 0 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 0 0 0 0 W Reset 0 0 0 0 Figure 2-60.
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Port Integration Module (S12GPIMV1) Table 2-88. PIE1AD Register Field Descriptions Field Description 7-0 PIE1AD Port AD interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. 1 Interrupt is enabled 0 Interrupt is disabled (interrupt flag masked) 2.4.3.
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Port Integration Module (S12GPIMV1) 2.4.3.64 Port AD Interrupt Flag Register (PIF1AD) Access: User read/write1 Address 0x027F 7 6 5 4 3 2 1 0 PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 0 0 0 0 0 0 0 0 R W Reset Figure 2-63. Port AD Interrupt Flag Register (PIF1AD) 1 Read: Anytime Write: Anytime Table 2-90.
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Port Integration Module (S12GPIMV1) 2.5 PIM Ports - Functional Description 2.5.1 General Each pin except BKGD can act as general-purpose I/O. In addition most pins can act as an output or input of a peripheral module. 2.5.2 Registers A set of configuration registers is common to all ports with exception of the ADC port (Table 2-91). All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pullup device.
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Port Integration Module (S12GPIMV1) 2.5.2.3 Data Direction Register (DDRx) This register defines whether the pin is used as an general-purpose input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-64). Independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address (2.5.2.1/2-249).
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Port Integration Module (S12GPIMV1) 2.5.2.6 Wired-Or Mode Register (WOMx) If the pin is used as an output this register turns off the active-high drive. This allows wired-or type connections of outputs. 2.5.2.7 Interrupt Enable Register (PIEx) If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 2.5.2.
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Port Integration Module (S12GPIMV1) Table 2-92.
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Port Integration Module (S12GPIMV1) Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not provided on these pins. 2.5.4.2 Pin Interrupts and Wakeup Ports P, J and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector.
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Port Integration Module (S12GPIMV1) 2.6 2.6.1 Initialization/Application Information Initialization After a system reset, software should: 1. Read the PKGCR and write to it with its preset content to engage the write lock on PKGCR[PKGCR2:PKGCR0] bits protecting the device from inadvertent changes to the pin layout in normal applications. 2. Write to PRR0 in 20 TSSOP to define the module routing and to PKGCR[APICLKS7] bit in any package for API_EXTCLK. GA240 / GA192 devices only: 3.
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Port Integration Module (S12GPIMV1) the ETRIG will be driven by the PWM internally. If the related PWM channel is not enabled, the ETRIG function will be triggered by other functions on the pin including general-purpose input. Table 2-94 illustrates the resulting trigger sources and their dependencies. Shaded fields apply to 20 TSSOP with shared ACMP analog input functions on port AD pins only. Table 2-94. ETRIG Sources 1 2 2.6.
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Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.
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Chapter 3 5V Analog Comparator (ACMPV1) Revision History Rev. No. (Item No.) Date (Submitted By) V00.08 13 Aug 2010 • Added register name to every bitfield reference V00.09 10 Sep 2010 • Internal updates • V01.00 18 Oct 2010 • Initial version • 3.1 Sections Affected Substantial Change(s) Introduction The analog comparator (ACMP) provides a circuit for comparing two analog input voltages. Refer to the device overview section for availability on a specific device. 3.
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5V Analog Comparator (ACMPV1) INTERNAL BUS ACIE ACDIEN (enable) ACE digital input buffer Control & Status Register ACO + ACMPM Hold _ ACOPE ACICE ACMOD ACMPP ACMP IRQ ACIF Sync SET ACIF Interrupt Control To Input Capture Channel ACMPO Figure 3-1. ACMP Block Diagram Figure 3-2. 3.4 External Signals The ACMP has two analog input signals, ACMPP and ACMPM, and one digital output, ACMPO. The associated pins are defined by the package option.
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5V Analog Comparator (ACMPV1) 3.6 Memory Map and Register Definition 3.6.1 Register Map Table 3-1 shows the ACMP register map. Table 3-1. ACMP Register Map Global Address Register Name 0x0260 ACMPC R W 0x0261 ACMPS R W Bit 7 6 5 4 3 2 ACIE ACOPE ACICE ACDIEN ACMOD1 ACMOD0 ACO 0 0 0 0 ACIF 1 0 0 Bit 0 ACE 0 = Unimplemented or Reserved 3.6.2 3.6.2.
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5V Analog Comparator (ACMPV1) Table 3-2. ACMPC Register Field Descriptions (continued) Field Description 5 ACICE ACMP Input Capture Enable— Establishes internal link to a timer input capture channel. When enabled, the associated timer pin is disconnected from the timer input. Refer to ACE description to account for initialization delay on this path.
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5V Analog Comparator (ACMPV1) Table 3-3. ACMPS Register Field Descriptions Field 7 ACIF Description ACMP Interrupt Flag— ACIF is set when a compare event occurs. Compare events are defined by ACMOD[1:0]. Writing a logic “1” to the bit field clears the flag. 0 Compare event has not occurred 1 Compare event has occurred 6 ACO 3.7 ACMP Output— Reading ACO returns the current value of the synchronized ACMP output. Refer to ACE description to account for initialization delay on this path.
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5V Analog Comparator (ACMPV1) MC9S12G Family Reference Manual, Rev.1.
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Chapter 4 Reference Voltage Attenuator (RVAV1) Revision History Rev. No. (Item No.) Date (Submitted By) V00.05 09 Jun 2010 • Added appendix title in note to reference reduced ADC clock • Orthographical corrections aligned to Freescale Publications Style Guide V00.06 01 Jul 2010 • Aligned to S12 register guidelines V01.00 18 Oct 2010 • Initial version 4.
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Reference Voltage Attenuator (RVAV1) STOP VRH RVAON RVA R VRH_INT 5R to ADC VRL_INT 4R VSSA Figure 4-1. RVA Module Block Diagram 4.4 External Signals The RVA has two external input signals, VRH and VSSA. 4.5 Modes of Operation 1. Attenuation Mode The RVA is attenuating the reference voltage when enabled by the register control bit and the MCU not being in STOP mode. 2. Bypass Mode The RVA is in bypass mode either when disabled or during STOP mode.
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Reference Voltage Attenuator (RVAV1) 4.6 Memory Map and Register Definition 4.6.1 Register Map Table 4-1 shows the RVA register map. Table 4-1. RVA Register Map Global Address Register Name 0x0276 RVACTL Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R W Bit 0 RVAON = Unimplemented or Reserved 4.6.2 4.6.2.1 Register Descriptions RVA Control Register (RVACTL) Access: User read/write1 Address 0x0276 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RVAON W Reset 0 0 0 0 0 0 0 0 Figure 4-2.
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Reference Voltage Attenuator (RVAV1) 4.7 Functional Description The RVA is a prescaler for the ADC reference voltage. If the attenuation is turned off the resistive divider is disconnected from VSSA, VRH_INT is connected to VRH and VRL_INT is connected to VSSA. In this mode the attenuation is bypassed and the resistive divider does not draw current. If the attenuation is turned on the resistive divider is connected to VSSA, VRH_INT and VRL_INT are connected to intermediate voltage levels: VRH_INT = 0.
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Chapter 5 S12G Memory Map Controller (S12GMMCV1) Table 5-1. Revision History Table Rev. No. Date (Item No.) (Submitted By) 01.02 5.1 20-May 2010 Sections Affected Substantial Change(s) Updates for S12VR48 and S12VR64 Introduction The S12GMMC module controls the access to all internal memories and peripherals for the CPU12 and S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip resources. Figure 5-1 shows a block diagram of the S12GMMC module. 5.1.
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S12G Memory Map Controller (S12GMMCV1) 5.1.3 Features The main features of this block are: • Paging capability to support a global 256 KByte memory address space • Bus arbitration between the masters CPU12, S12SBDM to different resources. • MCU operation mode control • MCU security control • Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 5.1.
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S12G Memory Map Controller (S12GMMCV1) CPU BDM MMC Address Decoder & Priority DBG Target Bus Controller EEPROM Flash RAM Peripherals Figure 5-1. S12GMMC Block Diagram 5.2 External Signal Description The S12GMMC uses two external pins to determine the devices operating mode: RESET and MODC (Figure 5-3) See Device User Guide (DUG) for the mapping of these signals to device pins. Table 5-3.
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S12G Memory Map Controller (S12GMMCV1) Address Register Name 0x000A Reserved Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 R W 0x000B MODE R MODC W 0x0010 Reserved R W 0x0011 DIRECT R W 0x0012 Reserved R W 0x0013 MMCCTL1 R W 0x0014 Reserved R NVMRES W 0x00
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S12G Memory Map Controller (S12GMMCV1) Read: Anytime. Write: Only if a transition is allowed (see Figure 5-4). The MODC bit of the MODE register is used to select the MCU’s operating mode. Table 5-4. MODE Field Descriptions Field Description 7 MODC Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external mode pin MODC determines the operating mode during RESET low (active).
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S12G Memory Map Controller (S12GMMCV1) Table 5-5. DIRECT Field Descriptions Field Description 7–0 DP[15:8] Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. These register bits form bits [15:8] of the local address (see Figure 5-6). Bit15 Bit8 Bit0 Bit7 DP [15:8] CPU Address [15:0] Figure 5-6. DIRECT Address Mapping Example 5-1. This example demonstrates usage of the Direct Addressing Mode MOVB #$04,DIRECT LDY <$12 5.3.2.
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S12G Memory Map Controller (S12GMMCV1) 5.3.2.4 Program Page Index Register (PPAGE) Address: 0x0015 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PIX3 PIX2 PIX1 PIX0 1 1 1 0 Figure 5-8. Program Page Index Register (PPAGE) Read: Anytime Write: Anytime The four index bits of the PPAGE register select a 16K page in the global memory map (Figure 5-11). The selected 16K page is mapped into the paging window ranging from local address 0x8000 to 0xBFFF.
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S12G Memory Map Controller (S12GMMCV1) The reset value of 0xE ensures that there is linear Flash space available between addresses 0x0000 and 0xFFFF out of reset. The fixed 16KB page from 0xC000-0xFFFF is the page number 0xF. 5.4 Functional Description The S12GMMC block performs several basic functions of the S12G sub-system operation: MCU operation modes, priority control, address mapping, select signal generation and access limitations for the system.
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S12G Memory Map Controller (S12GMMCV1) The page value for the program page window is stored in the PPAGE register. The value of the PPAGE register can be read or written by normal memory accesses as well as by the CALL and RTC instructions. Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64KB local CPU address space.
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S12G Memory Map Controller (S12GMMCV1) BDM HARDWARE COMMAND Global Address [17:0] Bit17 Bit0 Bit14 Bit13 BDMPPR Register [3:0] BDM Local Address [13:0] BDM FIRMWARE COMMAND Global Address [17:0] Bit17 Bit0 Bit14 Bit13 BDMPPR Register [3:0] CPU Local Address [13:0] Figure 5-10. MC9S12G Family Reference Manual, Rev.1.
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S12G Memory Map Controller (S12GMMCV1) Local CPU and BDM Memory Map Global Memory Map Register Space Register Space EEPROM EEPROM Flash Space Page 0xC Unimplemented RAM RAM 0x0000 0x0400 0x4000 NVMRES=0 Flash Space Page 0xD NVMRES=1 0x0_0000 0x0_0400 0x0_4000 Internal Flash NVM Space Resources Page 0x1 0x0_8000 0x8000 Paging Window Flash Space Page 0x2 0x3_0000 0xC000 Flash Space Flash Space Page 0xF Page 0xC 0x3_4000 0xFFFF Flash Space Page 0xD 0x3_8000 Flash Space Page 0xE
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S12G Memory Map Controller (S12GMMCV1) 5.4.3 Unimplemented and Reserved Address Ranges The S12GMMC is capable of mapping up 240K of flash, up to 4K of EEPROM and up to 11K of RAM into the global memory map. Smaller devices of the S12G-family do not utilize all of the available address space. Address ranges which are not associated with one of the on-chip memories fall into two categories: Unimplemented addresses and reserved addresses.
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S12G Memory Map Controller (S12GMMCV1) Table 5-8. Global Address Ranges S12GN16 S12GN32 0x040000x07FFF (NVMRES=1) S12G48, S12GN48 S12G64 S12G96 S12G128 S12G192 S12G240 Internal NVM Resources (for details refer to section FTMRG) 0x040000x07FFF (NVMRES=0) Reserved 0x080000x0FFFF 0x080000x1FFFF Unimplemented 0x200000x27FFF Reserved 0x280000x2FFFF 0x300000x33FFF Reserved 0x340000x37FFF 0x380000x3BFFF 0x3C0000x3FFFF 5.4.
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S12G Memory Map Controller (S12GMMCV1) MC9S12G Family Reference Manual, Rev.1.
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Chapter 6 Interrupt Module (S12SINTV1) Version Number Revision Date 01.02 13 Sep 2007 updates for S12P family devices: - re-added XIRQ and IRQ references since this functionality is used on devices without D2D - added low voltage reset as possible source to the pin reset vector 01.03 21 Nov 2007 added clarification of “Wake-up from STOP or WAIT by XIRQ with X bit set” feature 01.04 20 May 2009 added footnote about availability of “Wake-up from STOP or WAIT by XIRQ with X bit set” feature 6.
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Interrupt Module (S12SINTV1) • • • • • • • • 6.1.3 • • • • 6.1.4 2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2). I bit maskable interrupts can be nested. One X bit maskable interrupt vector request (at address vector base + 0x00F4). One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base + 0x00F6). One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
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Interrupt Module (S12SINTV1) Peripheral Interrupt Requests Wake Up CPU Priority Decoder Non I bit Maskable Channels To CPU Vector Address IVBR I bit Maskable Channels Interrupt Requests Figure 6-1. INT Block Diagram 6.2 External Signal Description The INT module has no external signals. 6.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the INT module. 6.3.
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Interrupt Module (S12SINTV1) Table 6-3. IVBR Field Descriptions Field Description 7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (that means vectors are located at 0xFF80–0xFFFE) to ensure compatibility to HCS12. Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset vector address.
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Interrupt Module (S12SINTV1) If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector.
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Interrupt Module (S12SINTV1) 6.5 6.5.1 Initialization/Application Information Initialization After system reset, software should: 1. Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF80–0xFFF9). 2. Enable I bit maskable interrupts by clearing the I bit in the CCR. 3. Enable the X bit maskable interrupt by clearing the X bit in the CCR. 6.5.
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Interrupt Module (S12SINTV1) If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the associated ISR is not called. The CPU then resumes program execution with the instruction following the WAI or STOP instruction.
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Interrupt Module (S12SINTV1) MC9S12G Family Reference Manual, Rev.1.
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Chapter 7 Background Debug Module (S12SBDMV1) Table 7-1. Revision History Sections Affected Revision Number Date 1.03 14.May.2009 Internal Conditional text only 1.04 30.Nov.2009 Internal Conditional text only 1.05 07.Dec.2010 Standardized format of revision history table header. 1.06 02.Mar.2011 7.1 7.3.2.2/7-295 7.2/7-291 Summary of Changes Corrected BPAE bit description.
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Background Debug Module (S12SBDMV1) • • • • • • • • • • GO_UNTIL command Hardware handshake protocol to increase the performance of the serial communication Active out of reset in special single chip mode Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 14 firmware commands execute from the standard BDM firmware lookup table Software control of BDM operation during wait mode When secured, hardware commands are allowed to access
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Background Debug Module (S12SBDMV1) 7.1.3 Block Diagram A block diagram of the BDM is shown in Figure 7-1. Host System BKGD Serial Interface Data 16-Bit Shift Register Control Register Block Address TRACE Instruction Code and Execution BDMACT Bus Interface and Control Logic Data Control Clocks ENBDM SDV Standard BDM Firmware LOOKUP TABLE UNSEC Secured BDM Firmware LOOKUP TABLE BDMSTS Register Figure 7-1. BDM Block Diagram 7.
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Background Debug Module (S12SBDMV1) Table 7-2. BDM Memory Map 7.3.2 Global Address Module Size (Bytes) 0x3_FF00–0x3_FF0B BDM registers 12 0x3_FF0C–0x3_FF0E BDM firmware ROM 3 0x3_FF0F Family ID (part of BDM firmware ROM) 1 0x3_FF10–0x3_FFFF BDM firmware ROM 240 Register Descriptions A summary of the registers associated with the BDM is shown in Figure 7-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
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Background Debug Module (S12SBDMV1) Global Address Register Name 0x3_FF08 BDMPPR Bit 7 R W 0x3_FF09 Reserved 6 5 4 0 0 0 0 0 0 0 0 0 0 BPAE R 3 2 1 Bit 0 BPP3 BPP2 BPP1 BPP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x3_FF0A Reserved R W 0x3_FF0B Reserved R W = Unimplemented, Reserved = Indeterminate X = Implemented (do not alter) = Always read zero 0 Figure 7-2. BDM Register Summary (continued) 7.3.2.
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Background Debug Module (S12SBDMV1) — All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution. Table 7-3. BDMSTS Field Descriptions Field Description 7 ENBDM Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed.
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Background Debug Module (S12SBDMV1) Register Global Address 0x3_FF06 7 6 5 4 3 2 1 0 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 Special Single-Chip Mode 1 1 0 0 1 0 0 0 All Other Modes 0 0 0 0 0 0 0 0 R W Reset Figure 7-4. BDM CCR Holding Register (BDMCCR) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured NOTE When BDM is made active, the CPU stores the content of its CCR register in the BDMCCR register.
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Background Debug Module (S12SBDMV1) 7.3.3 Family ID Assignment The family ID is an 8-bit value located in the BDM ROM in active BDM (at global address: 0x3_FF0F). The read-only value is a unique family ID which is 0xC2 for devices with an HCS12S core. 7.4 Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmware commands.
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Background Debug Module (S12SBDMV1) • • • Hardware BACKGROUND command CPU BGND instruction Breakpoint force or tag mechanism1 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
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Background Debug Module (S12SBDMV1) enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map. Table 7-5. Hardware Commands Opcode (hex) Data Description BACKGROUND 90 None Enter background mode if BDM is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed.
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Background Debug Module (S12SBDMV1) Table 7-6. Firmware Commands Command1 Opcode (hex) Data Description READ_NEXT2 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator. READ_X 65 16-bit data out Read X index register. READ_Y 66 16-bit data out Read Y index register. 67 16-bit data out Read stack pointer.
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Background Debug Module (S12SBDMV1) 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM ignores the least significant bit of the address and assumes an even address from the remaining bits. For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out.
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Background Debug Module (S12SBDMV1) Hardware Read 8 Bits AT ~16 TC/Bit 16 Bits AT ~16 TC/Bit Command Address 150-BC Delay 16 Bits AT ~16 TC/Bit Data Next Command 150-BC Delay Hardware Write Command Address Data Next Command 48-BC DELAY Firmware Read Command Next Command Data 36-BC DELAY Firmware Write Command Data Next Command 76-BC Delay GO, TRACE Command Next Command BC = Bus Clock Cycles TC = Target Clock Cycles Figure 7-6. BDM Command Structure 7.4.
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Background Debug Module (S12SBDMV1) earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 7-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time.
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Background Debug Module (S12SBDMV1) BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse High-Impedance High-Impedance High-Impedance Perceived Start of Bit Time R-C Rise BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit Figure 7-8. BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 7-9 shows the host receiving a logic 0 from the target.
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Background Debug Module (S12SBDMV1) 7.4.7 Serial Interface Hardware Handshake Protocol BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be modified when changing the settings for the VCO frequency (CPMUSYNR), it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The BDM clock frequency is always VCO frequency divided by 8.
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Background Debug Module (S12SBDMV1) Figure 7-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation.
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Background Debug Module (S12SBDMV1) NOTE The ACK pulse does not provide a time out. This means for the GO_UNTIL command that it can not be distinguished if a stop or wait has been executed (command discarded and ACK not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command. See the handshake abort procedure described in Section 7.4.
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Background Debug Module (S12SBDMV1) Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 7.4.9, “SYNC — Request Timed Reference Pulse”.
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Background Debug Module (S12SBDMV1) NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol.
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Background Debug Module (S12SBDMV1) 7.4.9 SYNC — Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1.
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Background Debug Module (S12SBDMV1) If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running.
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Background Debug Module (S12SBDMV1) handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles.
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Background Debug Module (S12SBDMV1) MC9S12G Family Reference Manual, Rev.1.
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Chapter 8 S12S Debug Module (S12SDBGV2) Table 8-1. Revision History Revision Number Revision Date Sections Affected 02.08 09.MAY.2008 General Spelling corrections. Revision history format changed. 02.09 29.MAY.2008 8.4.5.4 Added note for end aligned, PurePC, rollover case. 02.10 27.SEP.2012 General Changed cross reference formats 8.
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S12S Debug Module (S12SDBGV2) Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. 8.1.2 Overview The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated.
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S12S Debug Module (S12SDBGV2) • 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin and End alignment of tracing to trigger 8.1.4 Modes of Operation The DBG module can be used in all MCU functional modes. During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already armed, remains armed.
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S12S Debug Module (S12SDBGV2) 8.2 External Signal Description There are no external signals associated with this module. 8.3 8.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the DBG sub-block is shown in Figure 8-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
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S12S Debug Module (S12SDBGV2) Address Name 0x002C DBGADH 0x002D 0x002E 2 3 4 6 5 4 3 2 1 Bit 0 R W Bit 15 14 13 12 11 10 9 Bit 8 DBGADL R W Bit 7 6 5 4 3 2 1 Bit 0 DBGADHM R W Bit 15 14 13 12 11 10 9 Bit 8 1 Bit 0 R Bit 7 6 5 4 3 2 W This bit is visible at DBGCNT[7] and DBGSR[7] This represents the contents if the Comparator A control register is blended into this address.
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S12S Debug Module (S12SDBGV2) Table 8-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1.
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S12S Debug Module (S12SDBGV2) Address: 0x0021 R 7 6 5 4 3 2 1 0 TBF 0 0 0 0 SSF2 SSF1 SSF0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset POR = Unimplemented or Reserved Figure 8-4. Debug Status Register (DBGSR) Read: Anytime Write: Never Table 8-5. DBGSR Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed.
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S12S Debug Module (S12SDBGV2) Read: Anytime Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed. Table 8-7. DBGTCR Field Descriptions Field Description 6 TSOURCE Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is secured, this bit cannot be set and tracing is inhibited. This bit must be set to read the trace buffer.
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S12S Debug Module (S12SDBGV2) Table 8-10. ABCM Encoding 1 ABCM Description 00 Match0 mapped to comparator A match: Match1 mapped to comparator B match. 01 Match 0 mapped to comparator A/B inside range: Match1 disabled. 10 Match 0 mapped to comparator A/B outside range: Match1 disabled. 11 Reserved1 Currently defaults to Comparator A, Comparator B disabled 8.3.2.
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S12S Debug Module (S12SDBGV2) Read: Anytime Write: Never Table 8-12. DBGCNT Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
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S12S Debug Module (S12SDBGV2) Table 8-14. State Control Register Access Encoding 8.3.2.7.1 COMRV Visible State Control Register 01 DBGSCR2 10 DBGSCR3 11 DBGMFR Debug State Control Register 1 (DBGSCR1) Address: 0x0027 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 SC3 SC2 SC1 SC0 0 0 0 0 = Unimplemented or Reserved Figure 8-9. Debug State Control Register 1 (DBGSCR1) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG is not armed.
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S12S Debug Module (S12SDBGV2) Table 8-16. State1 Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 1010 1011 1100 1101 1110 1111 Reserved Reserved Reserved Either Match0 or Match2 to Final State........Match1 to State2 Reserved Reserved The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to final state has priority followed by the match on the lower channel number (0,1,2).
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S12S Debug Module (S12SDBGV2) Table 8-18. State2 —Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Match2 to Final State Match2 to State1..... Match0 to Final State Either Match0 or Match1 to Final State Reserved Reserved Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State3 Reserved Reserved Either Match0 or Match1 to Final State........
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S12S Debug Module (S12SDBGV2) Table 8-20. State3 — Sequencer Next State Selection SC[3:0] Description (Unspecified matches have no effect) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Match2 to State2........ Match1 to Final State Match0 to Final State....... Match1 to State1 Match1 to Final State....... Match2 to State1 Match1 to State2 Match1 to Final State Match2 to State2........
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S12S Debug Module (S12SDBGV2) register bytes (three address bus compare registers and a control register). Comparator C consists of four register bytes (three address bus compare registers and a control register). Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs from those of comparators A and C. Table 8-21.
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S12S Debug Module (S12SDBGV2) Read: DBGACTL if COMRV[1:0] = 00 DBGBCTL if COMRV[1:0] = 01 DBGCCTL if COMRV[1:0] = 10 Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed DBGBCTL if COMRV[1:0] = 01 and DBG not armed DBGCCTL if COMRV[1:0] = 10 and DBG not armed Table 8-22. DBGXCTL Field Descriptions Field Description 7 SZE (Comparators A and B) Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator.
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S12S Debug Module (S12SDBGV2) Table 8-23. Read or Write Comparison Logic Table 8.3.2.8.2 RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write data bus 1 0 1 No match 1 1 0 No match 1 1 1 Read data bus Debug Comparator Address High Register (DBGXAH) Address: 0x0029 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 Bit 17 Bit 16 0 0 = Unimplemented or Reserved Figure 8-16.
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S12S Debug Module (S12SDBGV2) 8.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM) Address: 0x002A R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-17. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 8-24 for visible register encoding. Write: If DBG not armed. See Table 8-24 for visible register encoding. Table 8-26.
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S12S Debug Module (S12SDBGV2) 8.3.2.8.5 Debug Comparator Data High Register (DBGADH) Address: 0x002C R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-19. Debug Comparator Data High Register (DBGADH) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 8-28.
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S12S Debug Module (S12SDBGV2) 8.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM) Address: 0x002E R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-21. Debug Comparator Data High Mask Register (DBGADHM) Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Table 8-30.
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S12S Debug Module (S12SDBGV2) 8.4.1 S12SDBG Operation Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity.
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S12S Debug Module (S12SDBGV2) All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (see Figure 8-23) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents.
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S12S Debug Module (S12SDBGV2) Table 8-32. Comparator C Access Considerations Condition For Valid Match 1 Comp C Address RWE RW Examples 0 X LDAA ADDR[n] STAA #$BYTE ADDR[n] ADDR[n] 1 0 STAA #$BYTE ADDR[n] ADDR[n] 1 1 LDAA #$BYTE ADDR[n] Read and write accesses of ADDR[n] 1 ADDR[n] Write accesses of ADDR[n] Read accesses of ADDR[n] A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code.
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S12S Debug Module (S12SDBGV2) SZE SZ DBGADHM, DBGADLM 0 X $FF00 Byte, data(ADDR[n])=DH Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match data( ADDR[n]) 0 X $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match data( ADDR[n+1]) 0 X $00FF Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL Possible unintended match 0 X $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data( ADDR[n], ADDR[n+1]) 0 X $FFFF Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL Possible unintended match 1 0 $0000 Wor
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S12S Debug Module (S12SDBGV2) range comparisons. The comparator B TAG bit is ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is ignored in range mode. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 8.4.2.2.
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S12S Debug Module (S12SDBGV2) 8.4.3.3 Immediate Trigger Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the session and issues a forced breakpoint request to the CPU.
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S12S Debug Module (S12SDBGV2) disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of comparator matches.
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S12S Debug Module (S12SDBGV2) 8.4.5.1.1 Storing with Begin Trigger Alignment Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger is stored in the Trace Buffer.
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S12S Debug Module (S12SDBGV2) In the following example an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place.
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S12S Debug Module (S12SDBGV2) storage. The information bits indicate the size of access (word or byte) and the type of access (read or write). When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle. 8.4.5.2.4 Compressed Pure PC Mode In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are stored. A compressed storage format is used to increase the effective depth of the trace buffer.
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S12S Debug Module (S12SDBGV2) 8.4.5.3.1 Information Bit Organization The format of the bits is dependent upon the active trace mode as described below. Field2 Bits in Detail Mode Bit 3 Bit 2 CSZ CRW Bit 1 Bit 0 ADDR[17] ADDR[16] Figure 8-25. Field2 Bits in Detail Mode In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU. Table 8-38.
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S12S Debug Module (S12SDBGV2) Table 8-39. PCH Field Descriptions (continued) Bit Description 0 PC16 Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16. 8.4.5.4 Trace Buffer Organization (Compressed Pure PC mode) Table 8-40.
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S12S Debug Module (S12SDBGV2) 8.4.5.5 Reading Data from Trace Buffer The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed.
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S12S Debug Module (S12SDBGV2) 8.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition. Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched address.
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S12S Debug Module (S12SDBGV2) Table 8-42. Breakpoint Setup For CPU Breakpoints 0 1 1 Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full 1 x 1 Terminate tracing and generate breakpoint immediately on trigger 1 x 0 Terminate tracing immediately on trigger 8.4.7.2 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the TALIGN bit.
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S12S Debug Module (S12SDBGV2) If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated breakpoint at the same address.
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S12S Debug Module (S12SDBGV2) 8.5.3 Scenario 2 A trigger is generated if a given sequence of 2 code events is executed. Figure 8-28. Scenario 2a SCR2=0101 SCR1=0011 State1 M1 M2 State2 Final State A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes. Figure 8-29.
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S12S Debug Module (S12SDBGV2) event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A cause a trigger. This is possible by using CompA and CompC to match on the same address as shown. Figure 8-32. Scenario 4a SCR1=0100 State1 M1 SCR3=0001 State 3 M0 State2 M2 M0 M1 M1 SCR2=0011 Final State This scenario is currently not possible using 2 comparators only.
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S12S Debug Module (S12SDBGV2) 8.5.6 Scenario 5 Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C. Figure 8-34. Scenario 5 SCR2=0110 SCR1=0011 M1 State1 M0 State2 Final State M2 Scenario 5 is possible with the S12SDBGV1 SCR encoding 8.5.7 Scenario 6 Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red.
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S12S Debug Module (S12SDBGV2) On simultaneous matches the lowest channel number has priority so with this configuration the forking from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a simultaneous match2/match1transitions to state2. 8.5.9 Scenario 8 Trigger when a routine/event at M2 follows either M1 or M0. Figure 8-37.
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S12S Debug Module (S12SDBGV2) is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third consecutive occurrence of event M0 without a reset M1. Figure 8-40. Scenario 10a M1 SCR1=0010 State1 M2 SCR2=0100 SCR3=0010 M2 State2 M0 State3 Final State M1 Figure 8-41. Scenario 10b M0 SCR2=0011 SCR1=0010 State1 M2 State2 SCR3=0000 M1 State3 Final State M0 Scenario 10b shows the case that after M2 then M1 must occur before M0.
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S12S Debug Module (S12SDBGV2) MC9S12G Family Reference Manual, Rev.1.
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Chapter 9 Security (S12XS9SECV2) Table 9-1. Revision History Revision Number Revision Date 02.00 27 Aug 2004 reviewed and updated for S12XD architecture 02.01 21 Feb 2007 added S12XE, S12XF and S12XS architectures 02.02 19 Apr 2007 corrected statement about Backdoor key access via BDM on XE, XF, XS 9.1 Sections Affected Description of Changes Introduction This specification describes the function of the security mechanism in the MC9S12G-Family (9SEC).
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Security (S12XS9SECV2) Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XS Unsecure Mode 2 9.1.3 SS ✔ NX ES EX ST NS SS ✔ ✔ ✔ NVM Commands 1 ✔ ✔ 1 ✔ ✔1 BDM ✔ ✔ — ✔2 DBG Module Trace ✔ ✔ — — EEPROM Array Access 1 NS Secure Mode NX ES EX ST Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information. BDM hardware commands restricted to peripheral registers only.
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Security (S12XS9SECV2) Table 9-4. Security Bits SEC[1:0] Security State 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured) NOTE Please refer to the Flash block guide for actual security configuration (in section “Flash Module Security”). 9.1.4 Operation of the Secured Microcontroller By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented.
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Security (S12XS9SECV2) memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked. 9.1.5 Unsecuring the Microcontroller Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2.
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Security (S12XS9SECV2) • • 9.1.7 The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte. The Flash sector containing the Flash options/security byte is not protected.
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Security (S12XS9SECV2) MC9S12G Family Reference Manual, Rev.1.
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Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU) Revision History Version Revision Effective Number Date Date Author Description of Changes V04.10 01 Jul 10 01 Jul 10 Added TC trimming to feature list V04.11 23 Aug 10 23 Aug 10 Removed feature of adaptive oscillator filter. Register bits 6 and 4to 0in the CPMUOSC register are marked reserved and do not alter. V04.12 27 April 12 27 April 12 10.
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S12 Clock, Reset and Power Management Unit (S12CPMU) • • • Dynamic gain control eliminates the need for external current limiting resistor Integrated resistor eliminates the need for external bias resistor. Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits power The Voltage Regulator (IVREG) has the following features: • Input voltage range from 3.13V to 5.
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S12 Clock, Reset and Power Management Unit (S12CPMU) — Loss of oscillation (clock monitor fail) — External pin RESET MC9S12G Family Reference Manual, Rev.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12CPMU. 10.1.2.1 Run Mode The voltage regulator is in Full Performance Mode (FPM). The Phase Locked Loop (PLL) is on. The Internal Reference Clock (IRC1M) is on. The API is available. • PLL Engaged Internal (PEI) — This is the default mode after System Reset and Power-On Reset. — The Bus Clock is based on the PLLCLK.
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S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.1.2.3 Stop Mode This mode is entered by executing the CPU STOP instruction. The voltage regulator is in Reduced Power Mode (RPM). The API is available. The Phase Locked Loop (PLL) is off. The Internal Reference Clock (IRC1M) is off. Core Clock, Bus Clock and BDM Clock are stopped.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.1.3 S12CPMU Block Diagram Illegal Address Access MMC VDD, VDDF (core supplies) Low Voltage Detect VDDA VDDR VSS ILAF LVDS Low Voltage Interrupt LVIE Low Voltage Detect VDDX VDDX VSSX Voltage Regulator 3.13 to 5.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Figure 10-2 shows a block diagram of the XOSCLCP. OSCCLK_LCP monitor fail Clock Monitor Peak Detector Gain Control VDD = 1.8 V VSS Rf Quartz Crystals EXTAL or Ceramic Resonators XTAL C1 C2 VSS VSS Figure 10-2. XOSCLCP Block Diagram MC9S12G Family Reference Manual, Rev.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.2 Signal Description This section lists and describes the signals that connect off chip. 10.2.1 RESET Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered. 10.2.2 EXTAL and XTAL These pins provide the interface for a crystal to control the internal clock generator circuitry.
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S12 Clock, Reset and Power Management Unit (S12CPMU) An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can improve the quality of this supply. NOTE Depending on the device package following device supply pins are maybe combined into one pin: VDDR, VDDX and VDDA. Depending on the device package following device supply pins are maybe combined into one pin: VSS, VSSX and VSSA.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the S12CPMU. 10.3.1 Module Memory Map The S12CPMU registers are shown in Figure 10-3.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Addres s Name Bit 7 6 5 ACLKTR5 ACLKTR4 ACLKTR3 APIR15 APIR14 APIR13 APIR12 APIR11 APIR7 APIR6 APIR5 APIR4 RESERVEDCP R MUTEST3 W 0 0 0 R 0 0 0 0x02F3 CPMUACLKTR 0x02F4 CPMUAPIRH 0x02F5 CPMUAPIRL 0x02F6 R W R W R W 0x02F7 RESERVED 0x02F8 CPMU IRCTRIMH W 0x02F9 CPMU IRCTRIML W 0x02FA CPMUOSC 4 3 2 1 Bit 0 0 0 APIR10 APIR9 APIR8 APIR3 APIR2 APIR1 APIR0 0 0 0 0 0 0 0 0 0 0 ACLKTR2 ACLKTR1 ACLK
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2 Register Descriptions This section describes all the S12CPMU registers and their individual bits. Address order is as listed in Figure 10-3. 10.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR) The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range. 0x0034 7 6 5 4 3 2 1 0 0 0 0 R VCOFRQ[1:0] SYNDIV[5:0] W Reset 0 1 0 1 1 Figure 10-4.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.2 S12CPMU Reference Divider Register (CPMUREFDIV) The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the external oscillator as reference. 0x0035 7 6 R 5 4 0 0 3 2 REFFRQ[1:0] 1 0 1 1 REFDIV[3:0] W Reset 0 0 0 0 1 1 Figure 10-5. S12CPMU Reference Divider Register (CPMUREFDIV) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register).
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV) The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK. 0x0036 R 7 6 5 0 0 0 4 3 2 1 0 1 1 2 1 0 ILAF OSCIF Note 3 0 POSTDIV[4:0] W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-6. S12CPMU Post Divider Register (CPMUPOSTDIV) Read: Anytime Write: Anytime if PLLSEL=1. Else write has no effect.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-3. CPMUFLG Field Descriptions Field Description 7 RTIF Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. 6 PORF Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT) This register enables S12CPMU interrupt requests. 0x0038 7 R 6 5 0 0 RTIE 4 3 2 0 0 LOCKIE 1 0 0 OSCIE W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-8. S12CPMU Interrupt Enable Register (CPMUINT) Read: Anytime Write: Anytime Table 10-4.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS) This register controls S12CPMU clock selection. 0x0039 7 6 PLLSEL PSTP 1 0 R 5 4 3 2 1 0 0 COP OSCSEL1 PRE PCE RTI OSCSEL COP OSCSEL0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 10-9. S12CPMU Clock Select Register (CPMUCLKS) Read: Anytime Write: 1. 2. 3. 4. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-5. CPMUCLKS Descriptions Field 7 PLLSEL Description PLL Select Bit This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock). PLLSEL can only be set to 0, if UPOSC=1. UPOSC= 0 sets the PLLSEL bit. Entering Full Stop Mode sets the PLLSEL bit. 0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, fbus = fosc / 2. 1 System clocks are derived from PLLCLK, fbus = fPLL / 2.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-5. CPMUCLKS Descriptions (continued) Field Description 1 RTI Clock Select — RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the RTIOSCSEL RTIOSCSEL bit re-starts the RTI time-out period. RTIOSCSEL can only be set to 1, if UPOSC=1. UPOSC= 0 clears the RTIOSCSEL bit. 0 RTI clock source is IRCCLK. 1 RTI clock source is OSCCLK.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.7 S12CPMU PLL Control Register (CPMUPLL) This register controls the PLL functionality. 0x003A R 7 6 0 0 5 4 FM1 FM0 0 0 3 2 1 0 0 0 0 0 0 0 0 0 W Reset 0 0 Figure 10-10. S12CPMU PLL Control Register (CPMUPLL) Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Write to this register clears the LOCK and UPOSC status bits.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.8 S12CPMU RTI Control Register (CPMURTI) This register selects the time-out period for the Real Time Interrupt. The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts in Stop Mode.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-10.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-11.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.9 S12CPMU COP Control Register (CPMUCOP) This register controls the COP (Computer Operating Properly) watchdog. The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit (see also Table 10-6). In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-12. CPMUCOP Field Descriptions Field Description 7 WCOP Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period generates a COP reset. As long as all writes occur during this window, $55 can be written as often as desired.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-14. COP Watchdog Rates if COPOSCSEL1=1 CR2 CR1 CR0 COPCLK Cycles to Time-out (COPCLK is ACLK internal RC-Oscillator clock) 0 0 0 COP disabled 0 0 1 27 0 1 0 29 0 1 1 2 11 1 0 0 2 13 1 0 1 2 15 1 1 0 2 16 1 1 1 2 17 MC9S12G Family Reference Manual, Rev.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.10 Reserved Register CPMUTEST0 NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU’s functionality. 0x003D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 10-13. Reserved Register (CPMUTEST0) Read: Anytime Write: Only in Special Mode 10.3.2.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP) This register is used to restart the COP time-out period. 0x003F R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Figure 10-15.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.13 Low Voltage Control Register (CPMULVCTL) The CPMULVCTL register allows the configuration of the low-voltage detect features. 0x02F1 R 7 6 5 4 3 2 0 0 0 0 0 LVDS 0 0 0 0 0 U W Reset 1 0 LVIE LVIF 0 U The Reset state of LVDS and LVIF depends on the external supplied VDDA level = Unimplemented or Reserved Figure 10-16.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL) The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features. 0x02F2 7 R W Reset APICLK 0 6 5 0 0 0 0 4 3 2 1 0 APIES APIEA APIFE APIE APIF 0 0 0 0 0 = Unimplemented or Reserved Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL) Read: Anytime Write: Anytime Table 10-16.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Figure 10-18. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) API min. period / 2 APIES=0 API period APIES=1 MC9S12G Family Reference Manual, Rev.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.15 Autonomous Clock Trimming Register (CPMUACLKTR) The CPMUACLKTR register configures the trimming of the Autonomous Clock (ACLK - trimmable internal RC-Oscillator) which can be selected as clock source for some CPMU features. 0x02F3 R W Reset 7 6 5 4 3 2 ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 F F F F F F 1 0 0 0 0 0 After de-assert of System Reset a value is automatically loaded from the Flash memory.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register (CPMUAPIRH / CPMUAPIRL) The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical interrupt rate. 0x02F4 R W Reset 7 6 5 4 3 2 1 0 APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-20.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-20. Selectable Autonomous Periodical Interrupt Periods 1 APICLK APIR[15:0] Selected Period 0 0000 0.2 ms1 0 0001 0.4 ms1 0 0002 0.6 ms1 0 0003 0.8 ms1 0 0004 1.0 ms1 0 0005 1.2 ms1 0 ..... ..... 0 FFFD 13106.8 ms1 0 FFFE 13107.0 ms1 0 FFFF 13107.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.17 Reserved Register CPMUTEST3 NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU’s functionality. 0x02F6 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 10-22.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.18 S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML) 0x02F8 15 14 13 12 11 R 10 9 8 0 TCTRIM[4:0] IRCTRIM[9:8] W Reset F F F F 0 0 F F After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIRC1M_TRIM. Figure 10-23.
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S12 Clock, Reset and Power Management Unit (S12CPMU) IRC1M frequency (IRCCLK) IRCTRIM[9:6] { 1.5MHz IRCTRIM[5:0] ...... 1MHz 600KHz IRCTRIM[9:0] $000 $3FF Figure 10-25. IRC1M Frequency Trimming Diagram MC9S12G Family Reference Manual, Rev.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) frequency 1 111 ] 4:0 [ RIM b1 =0 0b11111 ... 0b10101 0b10100 0b10011 0b10010 0b10001 T TC TC increases TCTRIM[4:0] = 0b10000 or 0b00000 (nominal TC) TCT RIM - 40C [4:0 ]=0 b01 111 0b00001 0b00010 0b00011 0b00100 0b00101 ... 0b01111 TC decreases 150C temperature Figure 10-26. Influence of TCTRIM[4:0] on the Temperature Coefficient NOTE The frequency is not necessarily linear with the temperature (in most cases it will not be).
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S12 Clock, Reset and Power Management Unit (S12CPMU) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 IRC1M indicative relative TC variation 0 (nominal TC of the IRC) -0.27% -0.54% -0.81% -1.08% -1.35% -1.63% -1.9% -2.20% -2.47% -2.77% -3.04 -3.33% IRC1M indicative frequency drift for relative TC variation 0% -0.5% -0.9% -1.3% -1.7% -2.0% -2.2% -2.5% -3.0% -3.4% -3.9% -4.3% -4.
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S12 Clock, Reset and Power Management Unit (S12CPMU) NOTE Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. Be aware that the output frequency vary with TC trimming. A frequency trimming correction is therefore necessary. The values provided in Table 10-23 are typical values at ambient temperature which can vary from device to device. 10.3.2.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-24. CPMUOSC Field Descriptions Field Description 7 OSCE Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source of the COP or RTI. A loss of oscillation will lead to a clock monitor reset. 0 External oscillator is disabled. REFCLK for PLL is IRCCLK. 1 External oscillator is enabled.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.20 S12CPMU Protection Register (CPMUPROT) This register protects the following clock configuration registers from accidental overwrite: CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and CPMUOSC 0x02FB R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PROT W Reset 0 0 0 0 0 0 0 0 Figure 10-28.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.3.2.21 Reserved Register CPMUTEST2 NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU’s functionality. 0x02FC R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 10-29.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.4 10.4.1 Functional Description Phase Locked Loop with Internal Filter (PLL) The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK. The REFCLK is by default the IRCCLK which is trimmed to fIRC1M_TRIM=1MHz. If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0] bits.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Several examples of PLL divider settings are shown in Table 10-25. The following rules help to achieve optimum stability and shortest lock time: • Use lowest possible fVCO / fREF ratio (SYNDIV value). • Use highest possible REFCLK frequency fREF. Table 10-25. Examples of PLL Divider Settings fosc REFDIV[3: 0] fREF off $00 1MHz 00 off $00 1MHz 4MHz $00 4MHz fVCO VCOFRQ[1:0] POSTDIV [4:0] fPLL fbus $18 50MHz 01 $03 12.5MHz 6.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.4.2 Startup from Reset An example of startup of clock system from Reset is given in Figure 10-30. Figure 10-30. Startup of clock system after Reset System Reset 768 cycles PLLCLK fPLL increasing fVCORST fPLL=32 MHz fPLL=16MHz )( tlock LOCK SYNDIV $18 (default target fVCO=50MHz) POSTDIV $03 (default target fPLL=fVCO/4 = 12.5MHz) CPU reset state 10.4.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 10-32. Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop Mode. Figure 10-32.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.4.5 10.4.5.1 External Oscillator Enabling the External Oscillator An example of how to use the oscillator as Bus Clock is shown in Figure 10-33. Figure 10-33. Enabling the External Oscillator enable external Oscillator by writing OSCE bit to one.
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S12 Clock, Reset and Power Management Unit (S12CPMU) 10.4.6 10.4.6.1 System Clock Configurations PLL Engaged Internal Mode (PEI) This mode is the default mode after System Reset or Power-On Reset. The Bus clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M). The PLL is configured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results in a PLLCLK of 12.5 MHz and a Bus clock of 6.25 MHz. The PLL can be re-configured to other bus frequencies.
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S12 Clock, Reset and Power Management Unit (S12CPMU) This mode can be entered from default mode PEI by performing the following steps: 1. Make sure the PLL configuration is valid. 2. Enable the external oscillator (OSCE bit) 3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1). 4. Clear all flags in the CPMUFLG register to be able to detect any status bit change. 5. Optionally status interrupts can be enabled (CPMUINT register). 6.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Table 10-27. Reset Vector Selection Sampled RESET Pin (256 cycles after release) Oscillator monitor fail pending COP time out pending 1 0 0 POR LVR Illegal Address Reset External pin RESET 1 1 X Clock Monitor Reset 1 0 1 COP Reset 0 X X POR LVR Illegal Address Reset External pin RESET Vector Fetch NOTE While System Reset is asserted the PLLCLK runs with the frequency fVCORST.
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S12 Clock, Reset and Power Management Unit (S12CPMU) generates a Clock Monitor Reset.In Full Stop Mode the external oscillator and the clock monitor are disabled. 10.5.2.2 Computer Operating Properly Watchdog (COP) Reset The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out.
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S12 Clock, Reset and Power Management Unit (S12CPMU) Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part. 10.5.3 Power-On Reset (POR) The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage level.
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S12 Clock, Reset and Power Management Unit (S12CPMU) The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the CPMURTI register. At the end of the RTI time-out period the RTIF flag is set to one and a new RTI time-out period starts immediately. A write to the CPMURTI register restarts the RTI time-out period. 10.6.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.
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S12 Clock, Reset and Power Management Unit (S12CPMU) COP is written at the correct time (due to independent API interrupt request) but the wrong value is written (alternating sequence of $55 and $AA is no longer maintained) which causes a COP reset. MC9S12G Family Reference Manual, Rev.1.
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S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.
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Chapter 11 Analog-to-Digital Converter (ADC10B8CV2) Revision History Version Number Revision Date Effective Date V02.00 13 May 2009 13 May 2009 Initial version copied from V01.05, changed unused Bits in ATDDIEN to read logic 1 Author Description of Changes V02.01 17 Dec 2009 17 Dec 2009 Updated Table 11-15 Analog Input Channel Select Coding description of internal channels. Updated register ATDDR (left/right justified result) description in section 11.3.2.12.1/11-438 and 11.3.2.12.
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Analog-to-Digital Converter (ADC10B8CV2) 11.1.1 • • • • • • • • • • • • • • Features 8-, 10-bit resolution. Automatic return to low power after conversion sequence Automatic compare with interrupt for higher than or less/equal than programmable value Programmable sample time. Left/right justified result data. External trigger control. Sequence complete interrupt. Analog input multiplexer for 8 analog input channels. Special conversions for VRH, VRL, (VRL+VRH)/2 and ADC temperature sensor.
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Analog-to-Digital Converter (ADC10B8CV2) 11.1.2 11.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 11.1.2.2 • • • MCU Operating Modes Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5.
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Analog-to-Digital Converter (ADC10B8CV2) 11.1.3 Block Diagram Bus Clock Clock Prescaler ATD Clock ETRIG0 ETRIG1 ETRIG2 Trigger Mux Mode and Sequence Complete Interrupt Compare Interrupt Timing Control ETRIG3 (See device specification for availability and connectivity) ATDCTL1 ATDDIEN VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 + Sample & Hold AN7 - AN6 AN5 Analog MUX Comparator AN4 AN3 AN2 AN1 AN0 Figure 11-1.
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Analog-to-Digital Converter (ADC10B8CV2) 11.2 Signal Description This section lists all inputs to the ADC10B8C block. 11.2.1 Detailed Signal Descriptions 11.2.1.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 11.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
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Analog-to-Digital Converter (ADC10B8CV2) Address 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C Name R ATDCTL3 W R ATDCTL4 W R ATDCTL5 W R ATDSTAT0 W R Unimplemented W R ATDCMPEH W R W R ATDSTAT2H W R ATDSTAT2L W R ATDDIENH W 6 5 4 3 2 1 Bit 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP2 SMP1 SMP0 SC SCAN MULT ETORF FIFOR 0 SCF 0 PRS[4:0] 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 0x001E ATD
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2 Register Descriptions This section describes in address order all the ADC10B8C registers and their individual bits. 11.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence. Module Base + 0x0000 7 R W Reserved Reset 0 6 5 4 0 0 0 0 0 0 3 2 1 0 WRAP3 WRAP2 WRAP1 WRAP0 1 1 1 1 = Unimplemented or Reserved Figure 11-3.
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Analog-to-Digital Converter (ADC10B8CV2) 1 If only AN0 should be converted use MULT=0. 11.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence. Module Base + 0x0001 7 6 5 4 3 2 1 0 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0 0 1 0 1 1 1 1 R W Reset Figure 11-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 11-3.
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Analog-to-Digital Converter (ADC10B8CV2) Table 11-5.
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Analog-to-Digital Converter (ADC10B8CV2) Table 11-6. ATDCTL2 Field Descriptions Field Description 6 AFFC ATD Fast Flag Clear All 0 ATD flag clearing done by write 1 to respective CCF[n] flag. 1 Changes all ATD conversion complete flags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag to clear automatically.
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2.4 ATD Control Register 3 (ATDCTL3) Writes to this register will abort current conversion sequence. Module Base + 0x0003 7 6 5 4 3 2 1 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 0 1 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 11-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 11-8.
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Analog-to-Digital Converter (ADC10B8CV2) Table 11-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 5.120 Volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 1 0 0 Reserved Reserved Table 11-10.
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Analog-to-Digital Converter (ADC10B8CV2) Table 11-11. ATD Behavior in Freeze Mode (Breakpoint) 11.3.2.5 FRZ1 FRZ0 Behavior in Freeze Mode 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 7 6 5 SMP2 SMP1 SMP0 0 0 0 4 3 2 1 0 0 1 R PRS[4:0] W Reset 0 0 1 Figure 11-7.
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2.6 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If the external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase.
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Analog-to-Digital Converter (ADC10B8CV2) Table 11-15.
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2.7 ATD Status Register 0 (ATDSTAT0) This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 R 6 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 11-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 11-16.
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Analog-to-Digital Converter (ADC10B8CV2) Table 11-16. ATDSTAT0 Field Descriptions (continued) Field Description 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6.
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[7:0]. Module Base + 0x000A R 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 CCF[7:0] W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-11. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime (for details see Table 11-18 below) Table 11-18.
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C R 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 6 5 4 2 1 0 0 0 0 IEN[7:0] W Reset 3 0 0 0 0 0 = Unimplemented or Reserved Figure 11-12. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 11-19.
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 8 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
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Analog-to-Digital Converter (ADC10B8CV2) 11.3.2.12.2 Right Justified Result Data (DJM=1) Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 R 15 14 13 12 0 0 0 0 0 0 0 0 11 10 9 8 7 5 4 3 2 1 0 0 0 0 0 0 Result-Bit[11:0] W Reset 6 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-15.
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Analog-to-Digital Converter (ADC10B8CV2) 11.4 Functional Description The ADC10B8C consists of an analog sub-block and a digital sub-block. 11.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 11.4.1.
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Analog-to-Digital Converter (ADC10B8CV2) or level sensitive with polarity control. Table 11-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register first and in the following enable the external trigger mode by bit ETRIGE.. Table 11-23.
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Analog-to-Digital Converter (ADC10B8CV2) This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC10B8C. 11.5 Resets At reset the ADC10B8C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 11.3.2, “Register Descriptions”) which details the registers and their bit-field. 11.
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Chapter 12 Analog-to-Digital Converter (ADC12B8CV2) Revision History Version Number Revision Date Effective Date V02.00 13 May 2009 13 May 2009 Initial version copied from V01.05, changed unused Bits in ATDDIEN to read logic 1 Author Description of Changes V02.01 17 Dec 2009 17 Dec 2009 Updated Table 12-15 Analog Input Channel Select Coding description of internal channels. Updated register ATDDR (left/right justified result) description in section 12.3.2.12.1/12-463 and 12.3.2.12.
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Analog-to-Digital Converter (ADC12B8CV2) 12.1.1 • • • • • • • • • • • • • • Features 8-, 10-, or 12-bit resolution. Automatic return to low power after conversion sequence Automatic compare with interrupt for higher than or less/equal than programmable value Programmable sample time. Left/right justified result data. External trigger control. Sequence complete interrupt. Analog input multiplexer for 8 analog input channels. Special conversions for VRH, VRL, (VRL+VRH)/2 and ADC temperature sensor.
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Analog-to-Digital Converter (ADC12B8CV2) 12.1.2 12.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 12.1.2.2 • • • MCU Operating Modes Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5.
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Analog-to-Digital Converter (ADC12B8CV2) 12.1.3 Block Diagram Bus Clock Clock Prescaler ATD Clock ETRIG0 ETRIG1 ETRIG2 Trigger Mux Mode and Sequence Complete Interrupt Compare Interrupt Timing Control ETRIG3 (See device specification for availability and connectivity) ATDCTL1 ATDDIEN VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 + Sample & Hold AN7 - AN6 AN5 Analog MUX Comparator AN4 AN3 AN2 AN1 AN0 Figure 12-1.
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Analog-to-Digital Converter (ADC12B8CV2) 12.2 Signal Description This section lists all inputs to the ADC12B8C block. 12.2.1 Detailed Signal Descriptions 12.2.1.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 12.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
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Analog-to-Digital Converter (ADC12B8CV2) Address 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C Name R ATDCTL3 W R ATDCTL4 W R ATDCTL5 W R ATDSTAT0 W R Unimplemented W R ATDCMPEH W R W R ATDSTAT2H W R ATDSTAT2L W R ATDDIENH W 6 5 4 3 2 1 Bit 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP2 SMP1 SMP0 SC SCAN MULT ETORF FIFOR 0 SCF 0 PRS[4:0] 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 0x001E ATD
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Analog-to-Digital Converter (ADC12B8CV2) 12.3.2 Register Descriptions This section describes in address order all the ADC12B8C registers and their individual bits. 12.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence. Module Base + 0x0000 7 R W Reserved Reset 0 6 5 4 0 0 0 0 0 0 3 2 1 0 WRAP3 WRAP2 WRAP1 WRAP0 1 1 1 1 = Unimplemented or Reserved Figure 12-3.
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Analog-to-Digital Converter (ADC12B8CV2) 1 If only AN0 should be converted use MULT=0. 12.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence. Module Base + 0x0001 7 6 5 4 3 2 1 0 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0 0 1 0 1 1 1 1 R W Reset Figure 12-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 12-3.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-5.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-6. ATDCTL2 Field Descriptions Field Description 6 AFFC ATD Fast Flag Clear All 0 ATD flag clearing done by write 1 to respective CCF[n] flag. 1 Changes all ATD conversion complete flags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag to clear automatically.
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Analog-to-Digital Converter (ADC12B8CV2) 12.3.2.4 ATD Control Register 3 (ATDCTL3) Writes to this register will abort current conversion sequence. Module Base + 0x0003 7 6 5 4 3 2 1 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 0 1 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 12-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 12-8.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 5.120 Volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 1 0 0 12-Bit Codes (transfer curve has 1.25mV offset) (resolution=1.25mV) 4095 ... 17 16 14 12 11 9 8 6 4 3 2 1 0 Table 12-10.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-11. ATD Behavior in Freeze Mode (Breakpoint) 12.3.2.5 FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 7 6 5 SMP2 SMP1 SMP0 0 0 0 4 3 2 1 0 0 1 R PRS[4:0] W Reset 0 0 1 Figure 12-7.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-13. Sample Time Select 12.3.2.6 SMP2 SMP1 SMP0 Sample Time in Number of ATD Clock Cycles 1 1 1 24 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If the external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-14. ATDCTL5 Field Descriptions (continued) Field Description 4 MULT Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-15. Analog Input Channel Select Coding Analog Input Channel SC CD CC CB CA 1 0 0 0 0 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1 0 1 0 0 VRH Internal_6, Temperature sense of ADC hardmacro 0 1 0 1 VRL 0 1 1 0 (VRH+VRL) / 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 1 0 1 1 Internal_5 1 1 X X Reserved MC9S12G Family Reference Manual, Rev.1.
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Analog-to-Digital Converter (ADC12B8CV2) 12.3.2.7 ATD Status Register 0 (ATDSTAT0) This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 6 R 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 12-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 12-16.
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Analog-to-Digital Converter (ADC12B8CV2) Table 12-16. ATDSTAT0 Field Descriptions (continued) Field Description 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6.
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Analog-to-Digital Converter (ADC12B8CV2) 12.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[7:0]. Module Base + 0x000A R 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 CCF[7:0] W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-11. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime (for details see Table 12-18 below) Table 12-18.
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Analog-to-Digital Converter (ADC12B8CV2) 12.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C R 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 6 5 4 2 1 0 0 0 0 IEN[7:0] W Reset 3 0 0 0 0 0 = Unimplemented or Reserved Figure 12-12. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 12-19.
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Analog-to-Digital Converter (ADC12B8CV2) 12.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 8 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
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Analog-to-Digital Converter (ADC12B8CV2) 12.3.2.12.2 Right Justified Result Data (DJM=1) Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 R 15 14 13 12 0 0 0 0 0 0 0 0 11 10 9 8 7 5 4 3 2 1 0 0 0 0 0 0 Result-Bit[11:0] W Reset 6 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-15.
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Analog-to-Digital Converter (ADC12B8CV2) 12.4 Functional Description The ADC12B8C consists of an analog sub-block and a digital sub-block. 12.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 12.4.1.
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Analog-to-Digital Converter (ADC12B8CV2) or level sensitive with polarity control. Table 12-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register first and in the following enable the external trigger mode by bit ETRIGE.. Table 12-23.
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Analog-to-Digital Converter (ADC12B8CV2) This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC12B8C. 12.5 Resets At reset the ADC12B8C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 12.3.2, “Register Descriptions”) which details the registers and their bit-field. 12.
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Analog-to-Digital Converter (ADC12B8CV2) MC9S12G Family Reference Manual, Rev.1.
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Chapter 13 Analog-to-Digital Converter (ADC10B12CV2) Revision History Version Number Revision Date Effective Date V02.00 13 May 2009 13 May 2009 Initial version copied from V01.06, changed unused Bits in ATDDIEN to read logic 1 Author Description of Changes V02.01 30.Nov 2009 30.Nov 2009 Updated Table 13-15 Analog Input Channel Select Coding description of internal channels. Updated register ATDDR (left/right justified result) description in section 13.3.2.12.1/13-489 and 13.3.2.12.
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Analog-to-Digital Converter (ADC10B12CV2) 13.1 Introduction The ADC10B12C is a 12-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 13.1.1 • • • • • • • • • • • • • • Features 8-, 10-bit resolution. Automatic return to low power after conversion sequence Automatic compare with interrupt for higher than or less/equal than programmable value Programmable sample time. Left/right justified result data.
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Analog-to-Digital Converter (ADC10B12CV2) 13.1.2 13.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 13.1.2.2 • • • MCU Operating Modes Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5.
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Analog-to-Digital Converter (ADC10B12CV2) 13.1.
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Analog-to-Digital Converter (ADC10B12CV2) 13.2 Signal Description This section lists all inputs to the ADC10B12C block. 13.2.1 Detailed Signal Descriptions 13.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 13.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
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Analog-to-Digital Converter (ADC10B12CV2) Address 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C Name R ATDCTL3 W R ATDCTL4 W R ATDCTL5 W R ATDSTAT0 W R Unimplemented W R ATDCMPEH W R W R ATDSTAT2H W R ATDSTAT2L W R ATDDIENH W 6 5 4 3 2 1 Bit 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP2 SMP1 SMP0 SC SCAN MULT ETORF FIFOR 0 SCF 0 PRS[4:0] 0 0 0 0 0 0 0 0 ATDCMPEL R W R 0x000E ATDCMPHTH W 0x000D Bit 7 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2
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Analog-to-Digital Converter (ADC10B12CV2) Address Name 0x0024 ATDDR10 0x0026 ATDDR11 0x0028 0x002F Unimplemented Bit 7 R W R W R 6 5 4 3 2 1 See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)” Bit 0 See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)” 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved Figure 13-2.
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Analog-to-Digital Converter (ADC10B12CV2) 13.3.2 Register Descriptions This section describes in address order all the ADC10B12C registers and their individual bits. 13.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence. Module Base + 0x0000 7 R W Reserved Reset 0 6 5 4 0 0 0 0 0 0 3 2 1 0 WRAP3 WRAP2 WRAP1 WRAP0 1 1 1 1 = Unimplemented or Reserved Figure 13-3.
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Analog-to-Digital Converter (ADC10B12CV2) 1 If only AN0 should be converted use MULT=0. 13.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence. Module Base + 0x0001 7 6 5 4 3 2 1 0 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0 0 1 0 1 1 1 1 R W Reset Figure 13-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 13-3.
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Analog-to-Digital Converter (ADC10B12CV2) Table 13-5.
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Analog-to-Digital Converter (ADC10B12CV2) Table 13-6. ATDCTL2 Field Descriptions Field Description 6 AFFC ATD Fast Flag Clear All 0 ATD flag clearing done by write 1 to respective CCF[n] flag. 1 Changes all ATD conversion complete flags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag to clear automatically.
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Analog-to-Digital Converter (ADC10B12CV2) 13.3.2.4 ATD Control Register 3 (ATDCTL3) Writes to this register will abort current conversion sequence. Module Base + 0x0003 7 6 5 4 3 2 1 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 0 1 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 13-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 13-8.
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Analog-to-Digital Converter (ADC10B12CV2) Table 13-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 5.120 Volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 1 0 0 Reserved Reserved Table 13-10.
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Analog-to-Digital Converter (ADC10B12CV2) Table 13-11. ATD Behavior in Freeze Mode (Breakpoint) 13.3.2.5 FRZ1 FRZ0 Behavior in Freeze Mode 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 7 6 5 SMP2 SMP1 SMP0 0 0 0 4 3 2 1 0 0 1 R PRS[4:0] W Reset 0 0 1 Figure 13-7.
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Analog-to-Digital Converter (ADC10B12CV2) 13.3.2.6 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If the external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase.
PAGE 482
Analog-to-Digital Converter (ADC10B12CV2) Table 13-15.
PAGE 483
Analog-to-Digital Converter (ADC10B12CV2) 13.3.2.7 ATD Status Register 0 (ATDSTAT0) This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 6 R 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 13-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 13-16.
PAGE 484
Analog-to-Digital Converter (ADC10B12CV2) Table 13-16. ATDSTAT0 Field Descriptions (continued) Field Description 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6.
PAGE 485
Analog-to-Digital Converter (ADC10B12CV2) 13.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[11:0]. Module Base + 0x000A R 15 14 13 12 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 CCF[11:0] W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-11. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime (for details see Table 13-18 below) Table 13-18.
PAGE 486
Analog-to-Digital Converter (ADC10B12CV2) 13.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C R 15 14 13 12 1 1 1 1 1 1 1 1 11 10 9 8 7 6 4 3 2 1 0 0 0 0 0 0 IEN[11:0] W Reset 5 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-12. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 13-19.
PAGE 487
Analog-to-Digital Converter (ADC10B12CV2) 13.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 12 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
PAGE 488
Analog-to-Digital Converter (ADC10B12CV2) 13.3.2.12.2 Right Justified Result Data (DJM=1) Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 R 15 14 13 12 0 0 0 0 0 0 0 0 11 10 9 8 7 5 4 3 2 1 0 0 0 0 0 0 Result-Bit[11:0] W Reset 6 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-15.
PAGE 489
Analog-to-Digital Converter (ADC10B12CV2) 13.4 Functional Description The ADC10B12C consists of an analog sub-block and a digital sub-block. 13.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 13.4.1.
PAGE 490
Analog-to-Digital Converter (ADC10B12CV2) edge or level sensitive with polarity control. Table 13-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register first and in the following enable the external trigger mode by bit ETRIGE. Table 13-23.
PAGE 491
Analog-to-Digital Converter (ADC10B12CV2) 13.5 Resets At reset the ADC10B12C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 13.3.2, “Register Descriptions”) which details the registers and their bit-field. 13.6 Interrupts The interrupts requested by the ADC10B12C are listed in Table 13-24. Refer to MCU specification for related vector address and priority. Table 13-24.
PAGE 492
Analog-to-Digital Converter (ADC10B12CV2) MC9S12G Family Reference Manual, Rev.1.
PAGE 493
Chapter 14 Analog-to-Digital Converter (ADC12B12CV2) Revision History Version Number Revision Date Effective Date V02.00 13 May 2009 13 May 2009 Initial version copied from V01.06, changed unused Bits in ATDDIEN to read logic 1 Author Description of Changes V02.01 30.Nov 2009 30.Nov 2009 Updated Table 14-15 Analog Input Channel Select Coding description of internal channels. Updated register ATDDR (left/right justified result) description in section 14.3.2.12.1/14-516 and 14.3.2.12.
PAGE 494
Analog-to-Digital Converter (ADC12B12CV2) 14.1 Introduction The ADC12B12C is a 12-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 14.1.1 • • • • • • • • • • • • • • Features 8-, 10-, or 12-bit resolution. Automatic return to low power after conversion sequence Automatic compare with interrupt for higher than or less/equal than programmable value Programmable sample time.
PAGE 495
Analog-to-Digital Converter (ADC12B12CV2) 14.1.2 14.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 14.1.2.2 • • • MCU Operating Modes Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5.
PAGE 496
Analog-to-Digital Converter (ADC12B12CV2) 14.1.
PAGE 497
Analog-to-Digital Converter (ADC12B12CV2) 14.2 Signal Description This section lists all inputs to the ADC12B12C block. 14.2.1 Detailed Signal Descriptions 14.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 14.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
PAGE 498
Analog-to-Digital Converter (ADC12B12CV2) Address 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C Name R ATDCTL3 W R ATDCTL4 W R ATDCTL5 W R ATDSTAT0 W R Unimplemented W R ATDCMPEH W R W R ATDSTAT2H W R ATDSTAT2L W R ATDDIENH W 6 5 4 3 2 1 Bit 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP2 SMP1 SMP0 SC SCAN MULT ETORF FIFOR 0 SCF 0 PRS[4:0] 0 0 0 0 0 0 0 0 ATDCMPEL R W R 0x000E ATDCMPHTH W 0x000D Bit 7 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2
PAGE 499
Analog-to-Digital Converter (ADC12B12CV2) Address Name 0x0024 ATDDR10 0x0026 ATDDR11 0x0028 0x002F Unimplemented Bit 7 R W R W R 6 5 4 3 2 1 See Section 14.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justified Result Data (DJM=1)” Bit 0 See Section 14.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justified Result Data (DJM=1)” 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved Figure 14-2.
PAGE 500
Analog-to-Digital Converter (ADC12B12CV2) 14.3.2 Register Descriptions This section describes in address order all the ADC12B12C registers and their individual bits. 14.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence. Module Base + 0x0000 7 R W Reserved Reset 0 6 5 4 0 0 0 0 0 0 3 2 1 0 WRAP3 WRAP2 WRAP1 WRAP0 1 1 1 1 = Unimplemented or Reserved Figure 14-3.
PAGE 501
Analog-to-Digital Converter (ADC12B12CV2) 1 If only AN0 should be converted use MULT=0. 14.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence. Module Base + 0x0001 7 6 5 4 3 2 1 0 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0 0 1 0 1 1 1 1 R W Reset Figure 14-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 14-3.
PAGE 502
Analog-to-Digital Converter (ADC12B12CV2) Table 14-5.
PAGE 503
Analog-to-Digital Converter (ADC12B12CV2) Table 14-6. ATDCTL2 Field Descriptions Field Description 6 AFFC ATD Fast Flag Clear All 0 ATD flag clearing done by write 1 to respective CCF[n] flag. 1 Changes all ATD conversion complete flags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag to clear automatically.
PAGE 504
Analog-to-Digital Converter (ADC12B12CV2) 14.3.2.4 ATD Control Register 3 (ATDCTL3) Writes to this register will abort current conversion sequence. Module Base + 0x0003 7 6 5 4 3 2 1 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 0 1 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 14-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 14-8.
PAGE 505
Analog-to-Digital Converter (ADC12B12CV2) Table 14-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 5.120 Volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 1 0 0 12-Bit Codes (transfer curve has 1.25mV offset) (resolution=1.25mV) 4095 ... 17 16 14 12 11 9 8 6 4 3 2 1 0 Table 14-10.
PAGE 506
Analog-to-Digital Converter (ADC12B12CV2) Table 14-11. ATD Behavior in Freeze Mode (Breakpoint) 14.3.2.5 FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 7 6 5 SMP2 SMP1 SMP0 0 0 0 4 3 2 1 0 0 1 R PRS[4:0] W Reset 0 0 1 Figure 14-7.
PAGE 507
Analog-to-Digital Converter (ADC12B12CV2) Table 14-13. Sample Time Select 14.3.2.6 SMP2 SMP1 SMP0 Sample Time in Number of ATD Clock Cycles 1 1 1 24 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If the external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
PAGE 508
Analog-to-Digital Converter (ADC12B12CV2) Table 14-14. ATDCTL5 Field Descriptions (continued) Field Description 4 MULT Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels.
PAGE 509
Analog-to-Digital Converter (ADC12B12CV2) Table 14-15. Analog Input Channel Select Coding Analog Input Channel SC CD CC CB CA 1 0 0 0 0 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1 0 1 0 0 VRH Internal_6, Temperature sense of ADC hardmacro 0 1 0 1 VRL 0 1 1 0 (VRH+VRL) / 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 1 0 1 1 Internal_5 1 1 X X Reserved MC9S12G Family Reference Manual, Rev.1.
PAGE 510
Analog-to-Digital Converter (ADC12B12CV2) 14.3.2.7 ATD Status Register 0 (ATDSTAT0) This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 R 6 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 14-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 14-16.
PAGE 511
Analog-to-Digital Converter (ADC12B12CV2) Table 14-16. ATDSTAT0 Field Descriptions (continued) Field Description 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6.
PAGE 512
Analog-to-Digital Converter (ADC12B12CV2) 14.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[11:0]. Module Base + 0x000A R 15 14 13 12 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 CCF[11:0] W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-11. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime (for details see Table 14-18 below) Table 14-18.
PAGE 513
Analog-to-Digital Converter (ADC12B12CV2) 14.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C R 15 14 13 12 1 1 1 1 1 1 1 1 11 10 9 8 7 6 4 3 2 1 0 0 0 0 0 0 IEN[11:0] W Reset 5 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-12. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 14-19.
PAGE 514
Analog-to-Digital Converter (ADC12B12CV2) 14.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 12 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
PAGE 515
Analog-to-Digital Converter (ADC12B12CV2) 14.3.2.12.2 Right Justified Result Data (DJM=1) Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 R 15 14 13 12 0 0 0 0 0 0 0 0 11 10 9 8 7 5 4 3 2 1 0 0 0 0 0 0 Result-Bit[11:0] W Reset 6 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-15.
PAGE 516
Analog-to-Digital Converter (ADC12B12CV2) 14.4 Functional Description The ADC12B12C consists of an analog sub-block and a digital sub-block. 14.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 14.4.1.
PAGE 517
Analog-to-Digital Converter (ADC12B12CV2) edge or level sensitive with polarity control. Table 14-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register first and in the following enable the external trigger mode by bit ETRIGE. Table 14-23.
PAGE 518
Analog-to-Digital Converter (ADC12B12CV2) 14.5 Resets At reset the ADC12B12C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 14.3.2, “Register Descriptions”) which details the registers and their bit-field. 14.6 Interrupts The interrupts requested by the ADC12B12C are listed in Table 14-24. Refer to MCU specification for related vector address and priority. Table 14-24.
PAGE 519
Chapter 15 Analog-to-Digital Converter (ADC10B16CV2) Revision History Version Number Revision Date Effective Date V02.00 18 June 2009 18 June 2009 Initial version copied 12 channel block guide Author Description of Changes V02.01 09 Feb 2010 09 Feb 2010 Updated Table 15-15 Analog Input Channel Select Coding description of internal channels. Updated register ATDDR (left/right justified result) description in section 15.3.2.12.1/15-541 and 15.3.2.12.
PAGE 520
Analog-to-Digital Converter (ADC10B16CV2) 15.1 Introduction The ADC10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 15.1.1 • • • • • • • • • • • • • • Features 8-, 10-bit resolution. Automatic return to low power after conversion sequence Automatic compare with interrupt for higher than or less/equal than programmable value Programmable sample time. Left/right justified result data.
PAGE 521
Analog-to-Digital Converter (ADC10B16CV2) 15.1.2 15.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 15.1.2.2 • • • MCU Operating Modes Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5.
PAGE 522
Analog-to-Digital Converter (ADC10B16CV2) 15.1.
PAGE 523
Analog-to-Digital Converter (ADC10B16CV2) 15.2 Signal Description This section lists all inputs to the ADC10B16C block. 15.2.1 Detailed Signal Descriptions 15.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 15.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
PAGE 524
Analog-to-Digital Converter (ADC10B16CV2) Address Name 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemented 0x0008 ATDCMPEH 0x0009 ATDCMPEL 0x000A ATDSTAT2H 0x000B ATDSTAT2L 0x000C ATDDIENH 0x000D ATDDIENL 0x000E ATDCMPHTH 0x000F ATDCMPHTL 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 0x001E ATDDR7 0x0020 ATDDR8 0x0022 ATDDR9 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R
PAGE 525
Analog-to-Digital Converter (ADC10B16CV2) Address Name 0x0024 ATDDR10 0x0026 ATDDR11 0x0028 ATDDR12 0x002A ATDDR13 0x002C ATDDR14 0x002E ATDDR15 Bit 7 R W R W R W R W R W R W W 6 5 4 3 2 1 See Section 15.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 15.3.2.12.2, “Right Justified Result Data (DJM=1)” Bit 0 See Section 15.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 15.3.2.12.2, “Right Justified Result Data (DJM=1)” See Section 15.3.2.12.
PAGE 526
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2 Register Descriptions This section describes in address order all the ADC10B16C registers and their individual bits. 15.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence. Module Base + 0x0000 7 R W Reserved Reset 0 6 5 4 0 0 0 0 0 0 3 2 1 0 WRAP3 WRAP2 WRAP1 WRAP0 1 1 1 1 = Unimplemented or Reserved Figure 15-3.
PAGE 527
Analog-to-Digital Converter (ADC10B16CV2) 1 If only AN0 should be converted use MULT=0. 15.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence. Module Base + 0x0001 7 6 5 4 3 2 1 0 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0 0 1 0 1 1 1 1 R W Reset Figure 15-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 15-3.
PAGE 528
Analog-to-Digital Converter (ADC10B16CV2) Table 15-5.
PAGE 529
Analog-to-Digital Converter (ADC10B16CV2) Table 15-6. ATDCTL2 Field Descriptions Field Description 6 AFFC ATD Fast Flag Clear All 0 ATD flag clearing done by write 1 to respective CCF[n] flag. 1 Changes all ATD conversion complete flags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag to clear automatically.
PAGE 530
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2.4 ATD Control Register 3 (ATDCTL3) Writes to this register will abort current conversion sequence. Module Base + 0x0003 7 6 5 4 3 2 1 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 0 1 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 15-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 15-8.
PAGE 531
Analog-to-Digital Converter (ADC10B16CV2) Table 15-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 5.120 Volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 1 0 0 Reserved Reserved Table 15-10.
PAGE 532
Analog-to-Digital Converter (ADC10B16CV2) Table 15-11. ATD Behavior in Freeze Mode (Breakpoint) 15.3.2.5 FRZ1 FRZ0 Behavior in Freeze Mode 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 7 6 5 SMP2 SMP1 SMP0 0 0 0 4 3 2 1 0 0 1 R PRS[4:0] W Reset 0 0 1 Figure 15-7.
PAGE 533
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2.6 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If the external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase.
PAGE 534
Analog-to-Digital Converter (ADC10B16CV2) Table 15-15.
PAGE 535
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2.7 ATD Status Register 0 (ATDSTAT0) This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 6 R 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 15-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 15-16.
PAGE 536
Analog-to-Digital Converter (ADC10B16CV2) Table 15-16. ATDSTAT0 Field Descriptions (continued) Field Description 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6.
PAGE 537
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[15:0]. Module Base + 0x000A 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CCF[15:0] W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 15-11. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime (for details see Table 15-18 below) Table 15-18.
PAGE 538
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 IEN[15:0] W Reset 8 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 15-12. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 15-19.
PAGE 539
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 16 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
PAGE 540
Analog-to-Digital Converter (ADC10B16CV2) 15.3.2.12.
PAGE 541
Analog-to-Digital Converter (ADC10B16CV2) 15.4 Functional Description The ADC10B16C consists of an analog sub-block and a digital sub-block. 15.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 15.4.1.
PAGE 542
Analog-to-Digital Converter (ADC10B16CV2) edge or level sensitive with polarity control. Table 15-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register first and in the following enable the external trigger mode by bit ETRIGE. Table 15-23.
PAGE 543
Analog-to-Digital Converter (ADC10B16CV2) 15.5 Resets At reset the ADC10B16C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 15.3.2, “Register Descriptions”) which details the registers and their bit-field. 15.6 Interrupts The interrupts requested by the ADC10B16C are listed in Table 15-24. Refer to MCU specification for related vector address and priority. Table 15-24.
PAGE 544
Analog-to-Digital Converter (ADC10B16CV2) MC9S12G Family Reference Manual, Rev.1.
PAGE 545
Chapter 16 Analog-to-Digital Converter (ADC12B16CV2) Revision History Version Number Revision Date Effective Date V02.00 18 June 2009 18 June 2009 Initial version copied 12 channel block guide Author Description of Changes V02.01 09 Feb 2010 09 Feb 2010 Updated Table 16-15 Analog Input Channel Select Coding description of internal channels. Updated register ATDDR (left/right justified result) description in section 16.3.2.12.1/16-568 and 16.3.2.12.
PAGE 546
Analog-to-Digital Converter (ADC12B16CV2) 16.1 Introduction The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 16.1.1 • • • • • • • • • • • • • • Features 8-, 10-, or 12-bit resolution. Automatic return to low power after conversion sequence Automatic compare with interrupt for higher than or less/equal than programmable value Programmable sample time.
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Analog-to-Digital Converter (ADC12B16CV2) 16.1.2 16.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 16.1.2.2 • • • MCU Operating Modes Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5.
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Analog-to-Digital Converter (ADC12B16CV2) 16.1.
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Analog-to-Digital Converter (ADC12B16CV2) 16.2 Signal Description This section lists all inputs to the ADC12B16C block. 16.2.1 Detailed Signal Descriptions 16.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 16.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
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Analog-to-Digital Converter (ADC12B16CV2) Address Name 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemented 0x0008 ATDCMPEH 0x0009 ATDCMPEL 0x000A ATDSTAT2H 0x000B ATDSTAT2L 0x000C ATDDIENH 0x000D ATDDIENL 0x000E ATDCMPHTH 0x000F ATDCMPHTL 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 0x001E ATDDR7 0x0020 ATDDR8 0x0022 ATDDR9 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R
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Analog-to-Digital Converter (ADC12B16CV2) Address Name 0x0024 ATDDR10 0x0026 ATDDR11 0x0028 ATDDR12 0x002A ATDDR13 0x002C ATDDR14 0x002E ATDDR15 Bit 7 R W R W R W R W R W R W W 6 5 4 3 2 1 See Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)” Bit 0 See Section 16.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 16.3.2.12.2, “Right Justified Result Data (DJM=1)” See Section 16.3.2.12.
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Analog-to-Digital Converter (ADC12B16CV2) 16.3.2 Register Descriptions This section describes in address order all the ADC12B16C registers and their individual bits. 16.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence. Module Base + 0x0000 7 R W Reserved Reset 0 6 5 4 0 0 0 0 0 0 3 2 1 0 WRAP3 WRAP2 WRAP1 WRAP0 1 1 1 1 = Unimplemented or Reserved Figure 16-3.
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Analog-to-Digital Converter (ADC12B16CV2) 1 If only AN0 should be converted use MULT=0. 16.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence. Module Base + 0x0001 7 6 5 4 3 2 1 0 ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 0 0 1 0 1 1 1 1 R W Reset Figure 16-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 16-3.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-5.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-6. ATDCTL2 Field Descriptions Field Description 6 AFFC ATD Fast Flag Clear All 0 ATD flag clearing done by write 1 to respective CCF[n] flag. 1 Changes all ATD conversion complete flags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag to clear automatically.
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Analog-to-Digital Converter (ADC12B16CV2) 16.3.2.4 ATD Control Register 3 (ATDCTL3) Writes to this register will abort current conversion sequence. Module Base + 0x0003 7 6 5 4 3 2 1 0 DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 0 1 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 16-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 16-8.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 5.120 Volts ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 ... 4 4 4 3 3 2 2 2 1 1 1 0 0 12-Bit Codes (transfer curve has 1.25mV offset) (resolution=1.25mV) 4095 ... 17 16 14 12 11 9 8 6 4 3 2 1 0 Table 16-10.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-11. ATD Behavior in Freeze Mode (Breakpoint) 16.3.2.5 FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately ATD Control Register 4 (ATDCTL4) Writes to this register will abort current conversion sequence. Module Base + 0x0004 7 6 5 SMP2 SMP1 SMP0 0 0 0 4 3 2 1 0 0 1 R PRS[4:0] W Reset 0 0 1 Figure 16-7.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-13. Sample Time Select 16.3.2.6 SMP2 SMP1 SMP0 Sample Time in Number of ATD Clock Cycles 1 1 1 24 ATD Control Register 5 (ATDCTL5) Writes to this register will abort current conversion sequence and start a new conversion sequence. If the external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-14. ATDCTL5 Field Descriptions (continued) Field Description 4 MULT Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-15. Analog Input Channel Select Coding Analog Input Channel SC CD CC CB CA 1 0 0 0 0 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1 0 1 0 0 VRH Internal_6, Temperature sense of ADC hardmacro 0 1 0 1 VRL 0 1 1 0 (VRH+VRL) / 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 1 0 1 1 Internal_5 1 1 X X Reserved MC9S12G Family Reference Manual, Rev.1.
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Analog-to-Digital Converter (ADC12B16CV2) 16.3.2.7 ATD Status Register 0 (ATDSTAT0) This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. Module Base + 0x0006 7 R 6 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 16-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 16-16.
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Analog-to-Digital Converter (ADC12B16CV2) Table 16-16. ATDSTAT0 Field Descriptions (continued) Field Description 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6.
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Analog-to-Digital Converter (ADC12B16CV2) 16.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[15:0]. Module Base + 0x000A 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CCF[15:0] W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-11. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime (for details see Table 16-18 below) Table 16-18.
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Analog-to-Digital Converter (ADC12B16CV2) 16.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 IEN[15:0] W Reset 8 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-12. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 16-19.
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Analog-to-Digital Converter (ADC12B16CV2) 16.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 16 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
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Analog-to-Digital Converter (ADC12B16CV2) 16.3.2.12.
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Analog-to-Digital Converter (ADC12B16CV2) 16.4 Functional Description The ADC12B16C consists of an analog sub-block and a digital sub-block. 16.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 16.4.1.
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Analog-to-Digital Converter (ADC12B16CV2) edge or level sensitive with polarity control. Table 16-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In order to avoid maybe false trigger events please enable the external digital input via ATDDIEN register first and in the following enable the external trigger mode by bit ETRIGE. Table 16-23.
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Analog-to-Digital Converter (ADC12B16CV2) 16.5 Resets At reset the ADC12B16C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 16.3.2, “Register Descriptions”) which details the registers and their bit-field. 16.6 Interrupts The interrupts requested by the ADC12B16C are listed in Table 16-24. Refer to MCU specification for related vector address and priority. Table 16-24.
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Chapter 17 Digital Analog Converter (DAC_8B5V) 17.1 Revision History Table 17-1. Revision History Table Rev. No. (Item No.) Data Sections Affected Substantial Change(s) 0.1 28-Oct.-09 all Initial Version 0.4 28-Oct.-09 (Thomas Becker) all Initial Version 0.5 12-Nov.-09 (Thomas Becker) all Reworked all sections, renamed pin names 0.6 17-Nov.-09 (Thomas Becker) 1.2.4 Added CPU stop mode 0.7 18-Nov.-09 (Thomas Becker) 1.2, 1.
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Digital Analog Converter (DAC_8B5V) Table 17-2. Terminology (continued) Term Meaning VRH High Reference Voltage FVR Full Voltage Range SSC Special Single Chip 17.2 Introduction The DAC_8B5V module is a digital to analog converter. The converter works with a resolution of 8 bit and generates an output voltage between VRL and VRH. The module consists of configuration registers and two analog functional units, a DAC resistor network and an operational amplifier.
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Digital Analog Converter (DAC_8B5V) If the “Unbuffered DAC” mode was used before entering stop mode, then the DACU pin will reach VRH voltage level during stop mode. The content of the configuration registers is unchanged. 17.2.3 Block Diagram S3 VRH DACU S1 AMPM S2 S2 – AMP + S1 AMPP DAC Resistor Network Operational Amplifier VRL Internal Bus Configuration Registers Figure 17-1. DAC_8B5V Block Diagram 17.
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Digital Analog Converter (DAC_8B5V) 17.3.4 AMPM Input Pin This analog pin is used as input for the operational amplifier negative input pin, if the according mode is selected. 17.4 Memory Map and Register Definition This sections provides the detailed information of all registers for the DAC_8B5V module. 17.4.1 Register Summary Figure 17-2 shows the summary of all implemented registers inside the DAC_8B5V module.
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Digital Analog Converter (DAC_8B5V) 17.4.2.1 Control Register (DACCTL) ) Access: User read/write1 Module Base + 0x0000 7 6 FVR DRIVE 1 0 R 5 4 3 0 0 0 2 1 0 DACM[2:0] W Reset 0 0 0 0 0 0 = Unimplemented Figure 17-3. Control Register (DACCTL) 1 Read: Anytime Write: Anytime Table 17-3. DACCTL Field Description Field 7 FVR 6 DRIVE Description Full Voltage Range — This bit defines the voltage range of the DAC.
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Digital Analog Converter (DAC_8B5V) 17.4.2.2 Analog Output Voltage Level Register (DACVOL) Access: User read/write1 Module Base + 0x0002 7 6 5 4 3 2 1 0 0 0 0 R VOLTAGE[7:0] W Reset 0 0 0 0 0 Figure 17-4. Analog Output Voltage Level Register (DACVOL) 1 Read: Anytime Write: Anytime Table 17-4. DACVOL Field Description Field Description 7:0 VOLTAGE — This register defines (together with the FVR bit) the analog output voltage.
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Digital Analog Converter (DAC_8B5V) Table 17-5.
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Digital Analog Converter (DAC_8B5V) 17.5.4 Mode “Unbuffered DAC” The “Unbuffered DAC” mode is selected by DACCNTL.DACM[2:0] = 0x4. During this mode the unbuffered analog voltage from the DAC resistor network output is available on the DACU output pin. The operational amplifier is disabled and the operational amplifier signals are disconnected from the AMP pins. For decoding of the control signals see Table 17-7. 17.5.
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Digital Analog Converter (DAC_8B5V) See Table 17-8 for an example for VRL = 0.0 V and VRH = 5.0 V. Table 17-8. Analog output voltage calculation FVR min. voltage max. voltage Resolution Equation 0 0.5V 4.484V 15.625mV VOLTAGE[7:0] x (4.0V) / 256) + 0.5V 1 0.0V 4.980V 19.531mV VOLTAGE[7:0] x (5.0V) / 256 MC9S12G Family Reference Manual, Rev.1.
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Digital Analog Converter (DAC_8B5V) MC9S12G Family Reference Manual, Rev.1.
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Digital Analog Converter (DAC_8B5V) MC9S12G Family Reference Manual, Rev.1.
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Digital Analog Converter (DAC_8B5V) MC9S12G Family Reference Manual, Rev.1.
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Chapter 18 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-1. Revision History Revision Number Revision Date V03.11 31 Mar 2009 V03.12 09 Aug 2010 Table 18-37 • Added ‘Bosch CAN 2.0A/B’ to bit time settings table V03.13 03 Mar 2011 Figure 18-4 Table 18-3 • Corrected CANE write restrictions • Removed footnote from RXFRM bit 18.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.1.1 Glossary Table 18-2. Terminology ACK Acknowledge of CAN message CAN Controller Area Network CRC Cyclic Redundancy Code EOF End of Frame FIFO First-In-First-Out Memory IFS Inter-Frame Sequence SOF Start of Frame CPU bus CPU related read/write data bus CAN bus CAN protocol related serial bus oscillator clock 18.1.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.1.3 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.2.2 TXCAN — CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state 18.2.3 CAN System A typical CAN system with MSCAN is shown in Figure 18-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) The detailed register descriptions follow in the order they appear in the register map.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x000E CANRXERR R 0x000F CANTXERR R 0x0010–0x0013 CANIDAR0–3 R 0x0014–0x0017 CANIDMRx R 0x0018–0x001B CANIDAR4–7 R 0x001C–0x001F CANIDMR4–7 R 0x0020–0x002F CANRXFG R 0x0030–0x003F CANTXFG R Bit 7 6 5 4 3 2 1 Bit 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write1 Module Base + 0x0000 7 R 6 5 RXACT RXFRM 4 3 2 1 0 TIME WUPE SLPRQ INITRQ 0 0 0 1 SYNCH CSWAI W Reset: 0 0 0 0 = Unimplemented Figure 18-4.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-3. CANCTL0 Register Field Descriptions (continued) 1 2 3 4 5 6 7 8 9 Field Description 2 WUPE3 Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode or from power down mode (entered from sleep) when traffic on CAN is detected (see Section 18.4.5.5, “MSCAN Sleep Mode”). This bit must be configured before sleep mode entry for the selected function to take effect.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write1 Module Base + 0x0001 7 6 5 4 3 2 CANE CLKSRC LOOPB LISTEN BORM WUPM 0 0 0 1 0 0 R 1 0 SLPAK INITAK 0 1 W Reset: = Unimplemented Figure 18-5.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-4. CANCTL1 Register Field Descriptions (continued) Field Description 1 SLPAK Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 18.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-7. Baud Rate Prescaler 18.3.2.4 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-9. Time Segment 2 Values 1 TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle1 0 0 1 2 Tq clock cycles : : : : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles This setting is not valid. Please refer to Table 18-37 for valid settings. Table 18-10.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 1 Read: Anytime Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Table 18-11.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-11. CANRFLG Register Field Descriptions (continued) Field Description 1 OVRIF Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected 0 RXF2 Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-12. CANRIER Register Field Descriptions Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write1 Module Base + 0x0006 R 7 6 5 4 3 0 0 0 0 0 2 1 0 TXE2 TXE1 TXE0 1 1 1 W Reset: 0 0 0 0 0 = Unimplemented Figure 18-10. MSCAN Transmitter Flag Register (CANTFLG) 1 Read: Anytime Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 1 Read: Anytime Write: Anytime when not in initialization mode NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 18-14. CANTIER Register Field Descriptions Field Description 2-0 TXEIE[2:0] 18.3.2.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Access: User read/write1 Module Base + 0x0009 R 7 6 5 4 3 2 1 0 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 18-13.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 18-17. CANTBSEL Register Field Descriptions Field Description 2-0 TX[2:0] Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-18. CANIDAC Register Field Descriptions Field Description 5-4 IDAM[1:0] Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 18.4.3, “Identifier Acceptance Filter”). Table 18-19 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 1 Read: Always reads zero in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special system operating modes can alter the MSCAN functionality. 18.3.2.14 MSCAN Miscellaneous Register (CANMISC) This register provides additional features.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. 18.3.2.16 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write1 Module Base + 0x0010 to Module Base + 0x0013 7 6 5 4 3 2 1 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 R W Reset Figure 18-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3 1 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 18-22.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write1 Module Base + 0x0014 to Module Base + 0x0017 7 6 5 4 3 2 1 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 R W Reset Figure 18-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3 1 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 18-24.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.3.3 Programmer’s Model of Message Storage The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 18-24.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 18-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued) Register Name Bit 7 6 5 4 3 2 1 Bit0 = Unused, always read ‘x’ Read: • For transmit buffers, anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping Module Base + 0x00X0 7 6 5 4 3 2 1 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 x x x x x x x x R W Reset: Figure 18-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping Table 18-27. IDR0 Register Field Descriptions — Extended Field Description 7-0 ID[28:21] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 7 6 5 4 3 2 1 0 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 x x x x x x x x R W Reset: Figure 18-28. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 18-29. IDR2 Register Field Descriptions — Extended Field Description 7-0 ID[14:7] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.3.3.1.2 IDR0–IDR3 for Standard Identifier Mapping Module Base + 0x00X0 7 6 5 4 3 2 1 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 x x x x x x x x R W Reset: Figure 18-30. Identifier Register 0 — Standard Mapping Table 18-31. IDR0 Register Field Descriptions — Standard Field Description 7-0 ID[10:3] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 18-32. Identifier Register 2 — Standard Mapping Module Base + 0x00X3 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 18-33. Identifier Register 3 — Standard Mapping 18.3.3.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00XC 7 6 5 4 3 2 1 0 DLC3 DLC2 DLC1 DLC0 x x x x R W Reset: x x x x = Unused; always read “x” Figure 18-35. Data Length Register (DLR) — Extended Identifier Mapping Table 18-34. DLR Register Field Descriptions Field Description 3-0 DLC[3:0] Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective message.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write1 Module Base + 0x00XD 7 6 5 4 3 2 1 0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 0 0 0 0 0 0 0 0 R W Reset: Figure 18-36. Transmit Buffer Priority Register (TBPR) 1 Read: Anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 18.3.2.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 1 Read: Anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Unimplemented 18.4 18.4.1 Functional Description General This section provides a complete functional description of the MSCAN. MC9S12G Family Reference Manual, Rev.1.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.4.2 Message Storage CAN Receive / Transmit Engine Memory Mapped I/O Rx0 RXF CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx4 Receiver TxBG Tx0 MSCAN TxFG Tx1 Transmitter TxBG Tx2 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 18-39. User Model for Message Buffer Organization The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 18.4.2.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) • • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 18.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) • • — The 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages. — The 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 18-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 18-41.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN. Eqn. 18-2 f CANCLK = ----------------------------------------------------Tq ( Prescaler value -) A bit time is subdivided into three segments as described in the Bosch CAN 2.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-36. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this period. SYNC_SEG Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.4.4.2 Special System Operating Modes The MSCAN module behaves as described within this specification in all special system operating modes. Write restrictions which exist on specific registers in normal modes are lifted for test purposes in special modes. 18.4.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like in normal system operating modes as described within this specification. 18.4.4.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Bus Clock Domain CAN Clock Domain INITRQ SYNC sync. INITRQ sync. SYNC INITAK CPU Init Request INITAK Flag INITAK INIT Flag Figure 18-45. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Figure 18-45).
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Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 18-38. CPU vs.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.4.5.5 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.4.5.7 Disabled Mode The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as specified. 18.4.5.8 Programmable Wake-Up Function The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0).
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.4.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer. 18.4.7.
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Freescale’s Scalable Controller Area Network (S12MSCANV3) 18.5 18.5.1 Initialization/Application Information MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode If the configuration of registers which are only writable in initialization mode shall be changed: 1.
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Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2) 19.1 Introduction The Version 2 of S12 PWM module is a channel scalable and optimized implementation of S12 PWM8B8C Version 1. The channel is scalable in pairs from PWM0 to PWM7 and the available channel number is 2, 4, 6 and 8. The shutdown feature has been removed and the flexibility to select one of four clock sources per channel has improved.
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Pulse-Width Modulator (S12PWM8B8CV2) 19.1.3 Block Diagram Figure 19-1 shows the block diagram for the 8-bit up to 8-channel scalable PWM block.
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Pulse-Width Modulator (S12PWM8B8CV2) 19.3 Memory Map and Register Definition 19.3.1 Module Memory Map This section describes the content of the registers in the scalable PWM module. The base address of the scalable PWM module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The figure below shows the registers associated with the scalable PWM and their relative offset from the base address.
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Pulse-Width Modulator (S12PWM8B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x0008 R PWMSCLA W Bit 7 6 5 4 3 2 1 Bit 0 0x0009 R PWMSCLB W Bit 7 6 5 4 3 2 1 Bit 0 0x000A R RESERVED W 0 0 0 0 0 0 0 0 0x000B R RESERVED W 0 0 0 0 0 0 0 0 0x000C R PWMCNT02 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R 0x000D PWMCNT12 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R 0x000E PWMCNT22 W Bit 7 6 5 4 3 2 1 Bit 0 0
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Pulse-Width Modulator (S12PWM8B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0016 R PWMPER22 W Bit 7 6 5 4 3 2 1 Bit 0 0x0017 R PWMPER32 W Bit 7 6 5 4 3 2 1 Bit 0 0x0018 R PWMPER42 W Bit 7 6 5 4 3 2 1 Bit 0 0x0019 R PWMPER52 W Bit 7 6 5 4 3 2 1 Bit 0 0x001A R PWMPER62 W Bit 7 6 5 4 3 2 1 Bit 0 0x001B R PWMPER72 W Bit 7 6 5 4 3 2 1 Bit 0 0x001C R PWMDTY02 W Bit 7 6 5 4 3 2 1 Bit 0 0x001D R PWMDTY12 W Bit 7 6 5 4 3 2 1 Bit 0 0x0
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Pulse-Width Modulator (S12PWM8B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0025 R RESERVED W 0 0 0 0 0 0 0 0 0x0026 R RESERVED W 0 0 0 0 0 0 0 0 0x0027 R RESERVED W 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 19-2. The scalable PWM Register Summary (Sheet 1 of 4) 1 The related bit is available only if corresponding channel exists. 2 The register is available only if corresponding channel exists. 19.3.2.
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Pulse-Width Modulator (S12PWM8B8CV2) Table 19-2. PWME Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7 PWME7 Pulse Width Channel 7 Enable 0 Pulse width channel 7 is disabled. 1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when its clock source begins its next cycle.
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Pulse-Width Modulator (S12PWM8B8CV2) Module Base + 0x0001 R W Reset 7 6 5 4 3 2 1 0 PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 0 0 0 0 0 0 0 0 Figure 19-4. PWM Polarity Register (PWMPOL) Read: Anytime Write: Anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition Table 19-3.
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Pulse-Width Modulator (S12PWM8B8CV2) Table 19-4. PWMCLK Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field 7-0 PCLK[7:0] Description Pulse Width Channel 7-0 Clock Select 0 Clock A or B is the clock source for PWM channel 7-0, as shown in Table 19-5 and Table 19-6. 1 Clock SA or SB is the clock source for PWM channel 7-0, as shown in Table 19-5 and Table 19-6.
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Pulse-Width Modulator (S12PWM8B8CV2) Table 19-7. PWMPRCLK Field Descriptions Field Description 6–4 PCKB[2:0] Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for all channels. These three bits determine the rate of clock B, as shown in Table 19-8. 2–0 PCKA[2:0] Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for all channels. These three bits determine the rate of clock A, as shown in Table 19-8. s Table 19-8.
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Pulse-Width Modulator (S12PWM8B8CV2) Table 19-9. PWMCAE Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field 7–0 CAE[7:0] 19.3.2.6 Description Center Aligned Output Modes on Channels 7–0 0 Channels 7–0 operate in left aligned output mode. 1 Channels 7–0 operate in center aligned output mode.
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Pulse-Width Modulator (S12PWM8B8CV2) Table 19-10. PWMCTL Field Descriptions Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7 CON67 Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8-bit PWMs. 1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte.
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Pulse-Width Modulator (S12PWM8B8CV2) Module Base + 0x00006 R W 7 6 5 4 3 2 1 0 PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 0 0 0 0 0 0 0 0 Reset Figure 19-9. PWM Clock Select Register (PWMCLKAB) Read: Anytime Write: Anytime NOTE Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 19-11.
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Pulse-Width Modulator (S12PWM8B8CV2) The clock source of each PWM channel is determined by PCLKx bits in PWMCLK (see Section 19.3.2.3, “PWM Clock Select Register (PWMCLK)) and PCLKABx bits in PWMCLKAB as shown in Table 19-5 and Table 19-6. 19.3.2.8 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two.
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Pulse-Width Modulator (S12PWM8B8CV2) 19.3.2.10 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0.
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Pulse-Width Modulator (S12PWM8B8CV2) • • The counter is written (counter resets to $00) The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written.
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Pulse-Width Modulator (S12PWM8B8CV2) • The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. See Section 19.4.
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Pulse-Width Modulator (S12PWM8B8CV2) 19.4 Functional Description 19.4.1 PWM Clock Select There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
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Pulse-Width Modulator (S12PWM8B8CV2) Clock A PCKA2 PCKA1 PCKA0 Clock A/2, A/4, A/6,....A/512 M U X Load PWMSCLA DIV 2 Clock to PWM Ch 0 PCLK0 PCLKAB0 Count = 1 8-Bit Down Counter M U X Clock SA PCLK1 PCLKAB1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 PCLKAB2 M U X 2 4 8 16 32 64 128 Divide by Prescaler Taps: X PCLK3 PCLKAB3 Clock B Clock B/2, B/4, B/6,....
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Pulse-Width Modulator (S12PWM8B8CV2) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register.
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Pulse-Width Modulator (S12PWM8B8CV2) 19.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period.
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Pulse-Width Modulator (S12PWM8B8CV2) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. 19.4.2.2 PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal.
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Pulse-Width Modulator (S12PWM8B8CV2) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops.
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Pulse-Width Modulator (S12PWM8B8CV2) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 19-17.
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Pulse-Width Modulator (S12PWM8B8CV2) 19.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 19-16.
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Pulse-Width Modulator (S12PWM8B8CV2) Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 19-20 is the output waveform generated. E = 100 ns E = 100 ns DUTY CYCLE = 75% PERIOD = 800 ns Figure 19-20. PWM Center Aligned Output Example Waveform 19.4.2.
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Pulse-Width Modulator (S12PWM8B8CV2) Clock Source 7 High Low PWMCNT6 PWMCNT7 Period/Duty Compare PWM7 Clock Source 5 High Low PWMCNT4 PWMCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWMCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWMCNT1 Period/Duty Compare PWM1 Maximum possible 16-bit channels Figure 19-21.
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Pulse-Width Modulator (S12PWM8B8CV2) In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect.
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Pulse-Width Modulator (S12PWM8B8CV2) • • 19.6 For channels 0, 1, 4, and 5 the clock choices are clock A. For channels 2, 3, 6, and 7 the clock choices are clock B. Interrupts The PWM module has no interrupt. MC9S12G Family Reference Manual, Rev.1.
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Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual, Rev.1.
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Chapter 20 Serial Communication Interface (S12SCIV5) Table 20-1. Revision History Version Revision Effective Number Date Date 05.03 12/25/2008 Author Description of Changes 05.04 08/05/2009 remove redundancy comments in Figure1-2 fix typo, SCIBDL reset value be 0x04, not 0x00 05.05 06/03/2010 fix typo, Table 20-4,SCICR1 Even parity should be PT=0 fix typo, on page 20-688,should be BKDIF,not BLDIF 20.
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Serial Communication Interface (S12SCIV5) 20.1.2 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
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Serial Communication Interface (S12SCIV5) 20.1.4 Block Diagram Figure 20-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks.
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Serial Communication Interface (S12SCIV5) 20.3.1 Module Memory Map and Register Definition The memory map for the SCI module is given below in Figure 20-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register. 20.3.2 Register Descriptions This section consists of register descriptions in address order.
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Serial Communication Interface (S12SCIV5) Register Name Bit 7 R 6 R8 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0x0006 SCIDRH W 0x0007 SCIDRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 T8 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 20-2. SCI Register Summary (Sheet 2 of 2) 20.3.2.
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Serial Communication Interface (S12SCIV5) Table 20-2. SCIBDH and SCIBDL Field Descriptions Field 7 IREN Description Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule. 0 IR disabled 1 IR enabled 6:5 TNP[1:0] Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. See Table 20-3. 4:0 7:0 SBR[12:0] SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register.
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Serial Communication Interface (S12SCIV5) Table 20-4. SCICR1 Field Descriptions Field Description 7 LOOPS Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit.
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Serial Communication Interface (S12SCIV5) 20.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Module Base + 0x0000 7 R W Reset RXEDGIF 0 6 5 4 3 2 0 0 0 0 BERRV 0 0 0 0 0 1 0 BERRIF BKDIF 0 0 = Unimplemented or Reserved Figure 20-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 20-6.
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Serial Communication Interface (S12SCIV5) Table 20-7. SCIACR1 Field Descriptions Field Description 7 RSEDGIE Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag, RXEDGIF, to generate interrupt requests. 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt requests enabled 1 BERRIE 0 BKDIE 20.3.2.5 Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt requests.
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Serial Communication Interface (S12SCIV5) Table 20-9. Bit Error Mode Coding 20.3.2.6 BERRM1 BERRM0 1 1 Function Reserved SCI Control Register 2 (SCICR2) Module Base + 0x0003 R W Reset 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 20-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 20-10.
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Serial Communication Interface (S12SCIV5) Table 20-10. SCICR2 Field Descriptions (continued) Field Description 1 RWU Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. 0 SBK Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set).
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Serial Communication Interface (S12SCIV5) Table 20-11. SCISR1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL).
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Serial Communication Interface (S12SCIV5) Table 20-11. SCISR1 Field Descriptions (continued) Field Description 1 FE Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL).
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Serial Communication Interface (S12SCIV5) Table 20-12. SCISR2 Field Descriptions (continued) Field Description 3 RXPOL Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity.
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Serial Communication Interface (S12SCIV5) Table 20-13. SCIDRH and SCIDRL Field Descriptions Field Description SCIDRH 7 R8 Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). SCIDRH 6 T8 Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
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Serial Communication Interface (S12SCIV5) R8 IREN SCI Data Register NF FE Ir_RXD Bus Clock Receive Shift Register SCRXD Receive and Wakeup Control PF RAF RE IDLE RWU RDRF LOOPS OR RSRC M Baud Rate Generator IDLE ILIE RDRF/OR Infrared Receive Decoder R16XCLK RXD RIE TIE WAKE Data Format Control ILT PE SBR12:SBR0 TDRE TDRE TC SCI Interrupt Request PT TC TCIE TE ÷16 Transmit Control LOOPS SBK RSRC T8 Transmit Shift Register RXEDGIE Active Edge Detect RXEDGIF BKDIF RXD SCI
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Serial Communication Interface (S12SCIV5) for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI.
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Serial Communication Interface (S12SCIV5) 8-Bit Data Format (Bit M in SCICR1 Clear) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Possible Parity Bit Bit 6 STOP Bit Bit 7 Next Start Bit Standard SCI Data Infrared SCI Data 9-Bit Data Format (Bit M in SCICR1 Set) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 POSSIBLE PARITY Bit Bit 6 Bit 7 Bit 8 STOP Bit NEXT START Bit Standard SCI Data Infrared SCI Data Figure 20-15.
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Serial Communication Interface (S12SCIV5) 20.4.4 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter.
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Serial Communication Interface (S12SCIV5) 20.4.
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Serial Communication Interface (S12SCIV5) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate.
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Serial Communication Interface (S12SCIV5) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out.
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Serial Communication Interface (S12SCIV5) Figure 20-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission.
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Serial Communication Interface (S12SCIV5) 20.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare RXD Pin Bit Error LIN Bus Bus Clock Sample Point Transmit Shift Register TXD Pin Figure 20-18.
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Serial Communication Interface (S12SCIV5) 20.4.
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Serial Communication Interface (S12SCIV5) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 20.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Serial Communication Interface (S12SCIV5) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 20-18 summarizes the results of the data bit samples. Table 20-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
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Serial Communication Interface (S12SCIV5) LSB Start Bit 0 0 0 0 0 0 RT10 1 RT9 RT1 1 RT8 RT1 1 RT7 0 RT1 1 RT1 1 RT5 1 RT1 Samples RT1 RXD 0 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT2 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 20-22. Start Bit Search Example 1 In Figure 20-23, verification sample at RT3 is high. The RT3 sample sets the noise flag.
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Serial Communication Interface (S12SCIV5) Perceived Start Bit LSB Actual Start Bit RT1 RT1 0 1 0 0 0 0 RT10 0 RT9 1 RT8 1 RT7 1 RT1 Samples RT1 RXD RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT16 RT15 RT14 RT13 RT12 RT11 RT6 RT5 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 20-24. Start Bit Search Example 3 Figure 20-25 shows the effect of noise early in the start bit time.
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Serial Communication Interface (S12SCIV5) Start Bit 0 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 0 1 1 0 0 0 0 0 0 0 0 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT1 1 RT7 1 RT1 RXD Samples LSB No Start Bit Found RT1 RT1 RT1 RT1 RT6 RT5 RT4 RT3 RT Clock Count RT2 RT Clock Reset RT Clock Figure 20-26. Start Bit Search Example 5 In Figure 20-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high.
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Serial Communication Interface (S12SCIV5) As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 20.4.6.5.1 Slow Data Tolerance Figure 20-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error.
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Serial Communication Interface (S12SCIV5) Stop Idle or Next Frame RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 Receiver RT Clock Data Samples Figure 20-29. Fast Data For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to finish data sampling of the stop bit.
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Serial Communication Interface (S12SCIV5) RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF.
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Serial Communication Interface (S12SCIV5) NOTE In single-wire operation data from the TXD pin is inverted if RXPOL is set. 20.4.8 Loop Operation In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI. Transmitter TXD Receiver RXD Figure 20-31. Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1).
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Serial Communication Interface (S12SCIV5) If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI. 20.5.2.3 Stop Mode The SCI is inactive during stop mode for reduced power consumption.
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Serial Communication Interface (S12SCIV5) new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL). 20.5.3.1.2 TC Description The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted.
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Serial Communication Interface (S12SCIV5) 20.5.3.1.8 BKDIF Description The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled. 20.5.4 Recovery from Wait Mode The SCI interrupt request can be used to bring the CPU out of wait mode. 20.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode.
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Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.
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Chapter 21 Serial Peripheral Interface (S12SPIV5) Revision History Revision Number Date 05.00 24 MAR 2005 21.1 Author Summary of Changes Added 16-bit transfer width feature. Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 21.1.1 Glossary of Terms SPI SS SCK MOSI MISO MOMI SISO 21.1.
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Serial Peripheral Interface (S12SPIV5) • • • Double-buffered data register Serial clock with programmable polarity and phase Control of SPI operation during wait mode 21.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. • Run mode This is the basic mode of operation. • Wait mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register.
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Serial Peripheral Interface (S12SPIV5) SPI 2 SPI Control Register 1 BIDIROE 2 SPI Control Register 2 SPC0 SPI Status Register SPIF MODF SPTEF Interrupt Control SPI Interrupt Request Baud Rate Generator Slave Control CPOL CPHA Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Master Control Counter Bus Clock Prescaler Clock Select SPPR 3 SPR MOSI Port Control Logic SCK SS Baud Rate Shift Clock Sample Clock 3 Shifter SPI Baud Rate Register Data
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Serial Peripheral Interface (S12SPIV5) 21.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. 21.2.
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Serial Peripheral Interface (S12SPIV5) Register Name 0x0005 SPIDRL R W 0x0006 Reserved R W 0x0007 Reserved R W Bit 7 6 5 4 3 2 1 Bit 0 R7 T7 R6 T6 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 = Unimplemented or Reserved Figure 21-2. SPI Register Summary 21.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number.
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Serial Peripheral Interface (S12SPIV5) Table 21-1. SPICR1 Field Descriptions Field Description 4 MSTR SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. 3 CPOL SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock.
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Serial Peripheral Interface (S12SPIV5) Table 21-3. SPICR2 Field Descriptions Field Description 6 XFRW Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Please refer to Section 21.3.2.
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Serial Peripheral Interface (S12SPIV5) 21.3.2.3 SPI Baud Rate Register (SPIBR) Module Base +0x0002 7 R 6 0 W Reset 0 5 4 3 SPPR2 SPPR1 SPPR0 0 0 0 0 0 2 1 0 SPR2 SPR1 SPR0 0 0 0 = Unimplemented or Reserved Figure 21-5. SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 21-5.
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Serial Peripheral Interface (S12SPIV5) Table 21-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 1 0 1 0 16 1.5625 Mbit/s 0 0 1 0 1 1 32 781.25 kbit/s 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 Mbit/s 0 1 0 0 0 1 12 2.08333 Mbit/s 0 1 0 0 1 0 24 1.
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Serial Peripheral Interface (S12SPIV5) Table 21-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 1 1 0 0 0 1 28 892.86 kbit/s 1 1 0 0 1 0 56 446.43 kbit/s 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s 1 1 0 1 0 1 448 55.80 kbit/s 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 Mbit/s 1 1 1 0 0 1 32 781.
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Serial Peripheral Interface (S12SPIV5) Table 21-7. SPISR Field Descriptions Field Description 5 SPTEF SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For information about clearing this bit and placing data into the transmit data register, please refer to Table 21-9. 0 SPI data register not empty. 1 SPI data register empty.
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Serial Peripheral Interface (S12SPIV5) 3 21.3.2.5 SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. SPI Data Register (SPIDR = SPIDRH:SPIDRL) Module Base +0x0004 7 6 5 4 3 2 1 0 R R15 R14 R13 R12 R11 R10 R9 R8 W T15 T14 T13 T12 T11 T10 T9 T8 0 0 0 0 0 0 0 0 Reset Figure 21-7.
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Serial Peripheral Interface (S12SPIV5) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data B Data A = Unspecified Data C = Reception in progress Figure 21-9. Reception with SPIF serviced in Time Data A Received Data B Received Data C Received Data B Lost SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data A = Unspecified Data C = Reception in progress Figure 21-10.
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Serial Peripheral Interface (S12SPIV5) The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1 register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions by the S-clock from the master, so data is exchanged between the master and the slave.
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Serial Peripheral Interface (S12SPIV5) If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs.
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Serial Peripheral Interface (S12SPIV5) NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves.
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Serial Peripheral Interface (S12SPIV5) 21.4.3.1 Clock Phase and Polarity Controls Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats.
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Serial Peripheral Interface (S12SPIV5) End of Idle State Begin 1 SCK Edge Number 2 3 4 5 6 7 8 Begin of Idle State End Transfer 9 10 11 12 13 14 15 16 Bit 1 Bit 6 LSB Minimum 1/2 SCK for tT, tl, tL MSB SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum lea
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Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) MSB first (LSBFE = 0) LSB first (LSBFE = 1) tL tT tI tL MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit
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Serial Peripheral Interface (S12SPIV5) A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
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Serial Peripheral Interface (S12SPIV5) End of Idle State Begin SCK Edge Number 1 2 3 4 End Transfer 5 6 7 8 9 10 11 12 13 14 Begin of Idle State 15 16 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL tI tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB tL = Mini
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Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tI tL Minimum 1/2 SCK for tT, tl, tL tL MSB first (LSBFE = 0) LSB first (LSBFE = 1) MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 B
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Serial Peripheral Interface (S12SPIV5) BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 21-3 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2.
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Serial Peripheral Interface (S12SPIV5) Table 21-10. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out Normal Mode SPC0 = 0 MOSI MOSI Serial In SPI SPI Serial In MISO Serial Out Bidirectional Mode SPC0 = 1 Slave Mode MSTR = 0 MOMI Serial Out MISO Serial In BIDIROE SPI BIDIROE Serial In SPI Serial Out SISO The direction of each serial I/O pin depends on the BIDIROE bit.
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Serial Peripheral Interface (S12SPIV5) the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state.
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Serial Peripheral Interface (S12SPIV5) NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode.
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Serial Peripheral Interface (S12SPIV5) 21.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 21.3.2.4, “SPI Status Register (SPISR)”. 21.4.7.5.3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced.
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Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.
PAGE 731
Chapter 22 Timer Module (TIM16B6CV3) Table 22-1. V03.00 Jan. 28, 2009 Initial version V03.01 Aug. 26, 2009 22.1.2/22-733 - Correct typo: TSCR ->TSCR1; 22.3.2.2/22-737, - Correct typo: ECTxxx->TIMxxx 22.4.3/22-749 V03.02 Apri,12,2010 22.3.2.6/22-740 -update TCRE bit description 22.3.2.9/22-742 22.4.3/22-749 V03.03 Jan,14,2013 22.
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Timer Module (TIM16B6CV3) Freeze: Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. 22.1.
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Timer Module (TIM16B6CV3) 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 22-2. Interrupt Flag Setting 22.2 External Signal Description The TIM16B6CV3 module has a selected number of external pins. Refer to device specification for exact number. 22.2.1 IOC5 - IOC0 — Input Capture and Output Compare Channel 5-0 Those pins serve as input capture or output compare for TIM16B6CV3 channel . NOTE For the description of interrupts see Section 22.6, “Interrupts”. 22.
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Timer Module (TIM16B6CV3) Only bits related to implemented channels are valid.
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Timer Module (TIM16B6CV3) 1 The register is available only if corresponding channel exists. 22.3.2.1 Timer Input Capture/Output Compare Select (TIOS) Module Base + 0x0000 7 6 5 4 3 2 1 0 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 0 0 0 0 0 R RESERVED RESERVED W Reset 0 0 Figure 22-4. Timer Input Capture/Output Compare Select (TIOS) Read: Anytime Write: Anytime Table 22-2. TIOS Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
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Timer Module (TIM16B6CV3) 22.3.2.3 Timer Count Register (TCNT) Module Base + 0x0004 15 14 13 12 11 10 9 9 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0 0 0 0 0 0 0 0 R W Reset Figure 22-6. Timer Count Register High (TCNTH) Module Base + 0x0005 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 R W Reset Figure 22-7. Timer Count Register Low (TCNTL) The 16-bit main timer is an up counter.
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Timer Module (TIM16B6CV3) Table 22-4. TSCR1 Field Descriptions Field Description 7 TEN Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is generated by the timer prescaler. 6 TSWAI Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait.
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Timer Module (TIM16B6CV3) Table 22-5. TTOV Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field Description 5:0 TOV[5:0] Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. 22.3.2.
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Timer Module (TIM16B6CV3) Table 22-7. Compare Result Output Action 22.3.2.7 OMx OLx Action 0 0 No output compare action on the timer output signal 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4) Module Base + 0x000A 7 6 5 4 3 2 1 0 EDG5B EDG5A EDG4B EDG4A 0 0 0 0 R RESERVED RESERVED RESERVED RESERVED W Reset 0 0 0 0 Figure 22-12.
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Timer Module (TIM16B6CV3) Table 22-9. Edge Detector Circuit Configuration 22.3.2.8 EDGnB EDGnA Configuration 1 1 Capture on any edge (rising or falling) Timer Interrupt Enable Register (TIE) Module Base + 0x000C 7 6 5 4 3 2 1 0 C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 R RESERVED RESERVED W Reset 0 0 Figure 22-14. Timer Interrupt Enable Register (TIE) Read: Anytime Write: Anytime. Table 22-10. TIE Field Descriptions Note: Writing to unavailable bits has no effect.
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Timer Module (TIM16B6CV3) Table 22-11. TSCR2 Field Descriptions Field 7 TOI 2 PR[2:0] Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set. Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 22-12. Table 22-12.
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Timer Module (TIM16B6CV3) Table 22-13. TRLG1 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field 5:0 C[5:0]F Description Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.
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Timer Module (TIM16B6CV3) 22.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0– 5(TCxH and TCxL) 0x0018=TC4H 0x001A=TC5H 0x001C=RESERVD 0x001E=RESERVD Module Base + 0x0010 = TC0H 0x0012 = TC1H 0x0014=TC2H 0x0016=TC3H 15 14 13 12 11 10 9 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 22-18.
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Timer Module (TIM16B6CV3) 22.3.2.13 Output Compare Pin Disconnect Register(OCPD) Module Base + 0x002C 7 6 5 4 3 2 1 0 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0 0 0 0 0 0 R RESERVED RESERVED W Reset 0 0 Figure 22-20. Output Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 22-15. OCPD Field Description Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
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Timer Module (TIM16B6CV3) ... Table 22-16. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 22-17 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
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Timer Module (TIM16B6CV3) PTPSR[7:0] CLK[1:0] PACLK PACLK/256 PACLK/65536 MUX PRNT Bus Clock PRE-PRESCALER PR[2:1:0] 1 MUX 0 PRESCALER CxI TCNT(hi):TCNT(lo) CxF 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 0 16-BIT COMPARATOR OM:OL0 TC0 EDG0A C0F C0F EDGE DETECT EDG0B CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0COMPARE TOV0 IOC0 PIN IOC0 CHANNEL 1 16-BIT COMPARATOR EDG1A C1F C1F OM:OL1 TC1 EDGE DETECT EDG1B CH. 1 CAPTURE IOC1 PIN LOGIC CH.
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Timer Module (TIM16B6CV3) By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by using PTPSR[7:0] bits of PTPSR register generating divide by 1, 2, 3, 4,....20, 21, 22, 23,......255, or 256. 22.4.2 Input Capture Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel.
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Timer Module (TIM16B6CV3) Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero. 22.5 Resets The reset state of each individual bit is listed within Section 22.3, “Memory Map and Register Definition” which details the registers and their bit fields 22.6 Interrupts This section describes interrupts originated by the TIM16B6CV3 block.
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Chapter 23 Timer Module (TIM16B8CV3) Table 23-1. V03.00 Jan. 28, 2009 V03.01 Aug. 26, 2009 23.1.2/23-752 Figure 23-4./23755 23.3.2.15/23-76 8 23.3.2.2/23-758, 23.3.2.3/23-758, 23.3.2.4/23-759, 23.4.3/23-774 V03.02 Apri,12,2010 23.3.2.8/23-762 -Add Table 23-10 23.3.2.11/23-76 -update TCRE bit description -add Figure 23-31 5 23.4.3/23-774 V03.03 Jan,14,2013 23.
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Timer Module (TIM16B8CV3) • • • • All channels have same input capture/output compare functionality. Clock prescaling. 16-bit counter. 16-bit pulse accumulator on channel 7 . 23.1.2 Modes of Operation Stop: Timer is off because clocks are stopped. Freeze: Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0. 23.1.
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Timer Module (TIM16B8CV3) Bus clock Prescaler 16-bit Counter Channel 0 Input capture Output compare Channel 1 Input capture Output compare Timer overflow interrupt Channel 2 Input capture Output compare Timer channel 0 interrupt Channel 3 Input capture Output compare Registers IOC0 IOC1 IOC2 IOC3 Channel 4 Input capture Output compare IOC4 Channel 5 Input capture Output compare Timer channel 7 interrupt Channel 6 Input capture Output compare PA overflow interrupt PA input interrupt IOC5 I
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Timer Module (TIM16B8CV3) TIMCLK (Timer clock) CLK1 CLK0 Intermodule Bus Clock select (PAMOD) Edge detector IOC7 PACLK PACLK / 256 PACLK / 65536 Prescaled clock (PCLK) 4:1 MUX Interrupt PACNT MUX Divide by 64 M clock Figure 23-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer IOCn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 23-3. Interrupt Flag Setting MC9S12G Family Reference Manual, Rev.1.
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Timer Module (TIM16B8CV3) PULSE ACCUMULATOR PAD CHANNEL 7 OUTPUT COMPARE OCPD TEN TIOS7 Figure 23-4. Channel 7 Output Compare/Pulse Accumulator Logic 23.2 External Signal Description The TIM16B8CV3 module has a selected number of external pins. Refer to device specification for exact number. 23.2.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7 . This can also be configured as pulse accumulator input. 23.2.
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Timer Module (TIM16B8CV3) 23.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Only bits related to implemented channels are valid.
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Timer Module (TIM16B8CV3) Register Name Bit 7 0x0021 PAFLG 0x0022 PACNTH 0x0023 PACNTL 0x0024–0x002B Reserved 0x002C OCPD 0x002D Reserved 0x002E PTPSR R 0 W R PACNT15 W R PACNT7 W R W R OCPD7 W R R W R W 0x002F Reserved PTPS7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 PAOVF PAIF PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Figure 23-
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Timer Module (TIM16B8CV3) 23.3.2.2 Timer Compare Force Register (CFORC) Module Base + 0x0001 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0 0 0 0 0 0 0 0 Reset Figure 23-7. Timer Compare Force Register (CFORC) Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 23-3. CFORC Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
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Timer Module (TIM16B8CV3) Table 23-4. OC7M Field Descriptions Field Description 7:0 OC7M[7:0] Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit.
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Timer Module (TIM16B8CV3) Module Base + 0x0005 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 R W Reset Figure 23-11. Timer Count Register Low (TCNTL) The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word.
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Timer Module (TIM16B8CV3) Table 23-6. TSCR1 Field Descriptions (continued) Field Description 5 TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally.
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Timer Module (TIM16B8CV3) 23.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 R W Reset Figure 23-14. Timer Control Register 1 (TCTL1) Module Base + 0x0009 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 R W Reset Figure 23-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 23-8.
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Timer Module (TIM16B8CV3) Note: To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in the OC7M register must also be cleared. The settings for these bits can be seen inTable 23-10. Table 23-10.
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Timer Module (TIM16B8CV3) Write: Anytime. Table 23-11. TCTL3/TCTL4 Field Descriptions Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero. Field 7:0 EDGnB EDGnA Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits. Table 23-12.
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Timer Module (TIM16B8CV3) 23.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R 6 5 4 0 0 0 TOI 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 23-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. Table 23-14. TSCR2 Field Descriptions Field 7 TOI Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set.
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Timer Module (TIM16B8CV3) NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 23.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E 7 6 5 4 3 2 1 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 R W Reset Figure 23-20. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared).
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Timer Module (TIM16B8CV3) Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set. Table 23-17. TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one (See also TCRE control bit explanation.) 23.3.2.
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Timer Module (TIM16B8CV3) 23.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 7 R 6 5 4 3 2 1 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 0 W Reset 0 Unimplemented or Reserved Figure 23-24. 16-Bit Pulse Accumulator Control Register (PACTL) Read: Any time Write: Any time When PAEN is set, the Pulse Accumulator counter is enabled. The Pulse Accumulator counter shares the input pin with IOC7. Table 23-18.
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Timer Module (TIM16B8CV3) Table 23-19. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div. by 64 clock enabled with pin high level 1 1 Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the ÷64 clock is generated by the timer prescaler. Table 23-20.
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Timer Module (TIM16B8CV3) Table 23-21. PAFLG Field Descriptions Field Description 1 PAOVF Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one. 0 PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.
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Timer Module (TIM16B8CV3) 23.3.2.18 Output Compare Pin Disconnect Register(OCPD) Module Base + 0x002C 7 6 5 4 3 2 1 0 OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0 0 0 0 0 0 0 0 R W Reset Figure 23-28. Output Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 23-22. OCPD Field Description Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
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Timer Module (TIM16B8CV3) ... Table 23-23. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 23-24 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
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Timer Module (TIM16B8CV3) PTPSR[7:0] CLK[1:0] PACLK PACLK/256 PACLK/65536 MUX PRNT Bus Clock PRE-PRESCALER PR[2:1:0] channel 7 output compare 1 MUX 0 PRESCALER TCRE CxI TCNT(hi):TCNT(lo) CxF CLEAR COUNTER 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 0 16-BIT COMPARATOR C0F C0F OM:OL0 TC0 EDG0A TOV0 EDGE DETECT EDG0B CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0COMPARE IOC0 PIN IOC0 CHANNEL 1 16-BIT COMPARATOR C1F C1F OM:OL1 TC1 EDG1A EDGE DETECT EDG1B CH.
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Timer Module (TIM16B8CV3) 23.4.1 Prescaler The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled.
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Timer Module (TIM16B8CV3) Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it will last only one bus cycle then reset to 0.
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Timer Module (TIM16B8CV3) 23.4.5 Event Counter Mode Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7 pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to increment the count. NOTE The PACNT input and timer channel 7 use the same pin IOC7. To use the IOC7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7.
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Timer Module (TIM16B8CV3) Table 23-25. TIM16B8CV3 Interrupts Interrupt Offset Vector Priority Source Description C[7:0]F — — — Timer Channel 7–0 Active high timer channel interrupts 7–0 PAOVI — — — Pulse Accumulator Input Active high pulse accumulator input interrupt PAOVF — — — Pulse Accumulator Overflow Pulse accumulator overflow interrupt TOF — — — Timer Overflow Timer Overflow interrupt The TIM16B8CV3 could use up to 11 interrupt vectors.
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Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual, Rev.1.
PAGE 777
Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1) Table 24-1. Revision History Revision Number Revision Date V01.04 17 Jun 2010 24.4.6.1/24-809 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] 24.4.6.2/24-810 of the register FSTAT. 24.4.6.3/24-810 24.4.6.14/24-82 0 V01.05 20 aug 2010 24.4.6.2/24-810 Updated description of the commands RD1BLK, MLOADU and MLOADF 24.4.6.12/24-81 7 24.4.6.13/24-81 9 Rev.1.23 31 Jan 2011 24.3.2.
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The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
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16 KByte Flash Module (S12FTMRG16K1V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 24.1.2.
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16 KByte Flash Module (S12FTMRG16K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 4Kx39 sector 0 sector 1 Protection sector 31 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 256x22 sector 0 sector 1 sector 127 Figure 24-1. FTMRG16K1 Block Diagram 24.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual, Rev.1.
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16 KByte Flash Module (S12FTMRG16K1V1) 24.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
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16 KByte Flash Module (S12FTMRG16K1V1) The FPROT register, described in Section 24.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Two separate memory regions, one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID1 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 24.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 24.4.2 Table 24-6.
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16 KByte Flash Module (S12FTMRG16K1V1) 0x0_4000 P-Flash IFR 1 Kbyte (NVMRES=1) 0x0_4400 Reserved 5k bytes RAM Start = 0x0_5800 RAM End = 0x0_59FF Reserved 512 bytes Reserved 4608 bytes 0x0_6C00 Reserved 5120 bytes 0x0_7FFF Figure 24-3. Memory Controller Resource Memory Map (NVMRES=1) 24.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013.
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16 KByte Flash Module (S12FTMRG16K1V1) Address & Name 0x0003 FRSV0 0x0004 FCNFG 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EEPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FDFD FSFD DFDIE SFDIE MGSTAT1 MGSTAT0 DFDIF SFDIF W R CCIE IGNSF W R 0 0 0 0 0 0 W R 0 CCIF ACCERR FPVIOL 0 0 MGBUSY RSVD 0 0 W R 0 0 W R RNV6 FPOPEN FPHDIS FPHS1 FPHS0
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16 KByte Flash Module (S12FTMRG16K1V1) Address & Name 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W = Unimplemented or Reserved Figure 24-4. FTMRG16K1 Register Summary (continued) 24.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-7. FCLKDIV Field Descriptions (continued) Field Description 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in normal mode. 5–0 FDIV[5:0] Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms.
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16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 24-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable.
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16 KByte Flash Module (S12FTMRG16K1V1) The security function in the Flash module is described in Section 24.5. 24.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations. Offset Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 2 1 0 CCOBIX[2:0] W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 24-7.
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16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 24-9. Flash Configuration Register (FCNFG) CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not writable. Table 24-13.
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16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DFDIE SFDIE 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 24-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 24-14.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF.
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16 KByte Flash Module (S12FTMRG16K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 24-17.
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16 KByte Flash Module (S12FTMRG16K1V1) 24.3.2.10 EEPROM Protection Register (EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. Offset Module Base + 0x0009 7 R 6 5 0 0 4 3 DPOPEN 2 1 0 F1 F1 DPS[4:0] W Reset F1 0 0 F1 F1 F1 = Unimplemented or Reserved Figure 24-14. EEPROM Protection Register (EEPROT) 1 Loaded from IFR Flash configuration field, during reset sequence.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-21. EEPROM Protection Address Range DPS[4:0] Global Address Range Protected Size 00000 0x0_0400 – 0x0_041F 32 bytes 00001 0x0_0400 – 0x0_043F 64 bytes 00010 0x0_0400 – 0x0_045F 96 bytes 00011 0x0_0400 – 0x0_047F 128 bytes 00100 0x0_0400 – 0x0_049F 160 bytes 00101 0x0_0400 – 0x0_04BF 192 bytes The Protection Size goes on enlarging in step of 32 bytes, for each DPS value increasing of one. . . .
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16 KByte Flash Module (S12FTMRG16K1V1) the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes (as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the FCCOB register array.
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16 KByte Flash Module (S12FTMRG16K1V1) 24.3.2.13 Flash Reserved2 Register (FRSV2) This Flash register is reserved for factory testing. Offset Module Base + 0x000D R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-18. Flash Reserved2 Register (FRSV2) All bits in the FRSV2 register read 0 and are not writable. 24.3.2.14 Flash Reserved3 Register (FRSV3) This Flash register is reserved for factory testing.
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16 KByte Flash Module (S12FTMRG16K1V1) 24.3.2.16 Flash Option Register (FOPT) The FOPT register is the Flash option register. Offset Module Base + 0x0010 7 6 5 4 R 3 2 1 0 F1 F1 F1 F1 NV[7:0] W Reset F1 F1 F1 F1 = Unimplemented or Reserved Figure 24-21. Flash Option Register (FOPT) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FOPT register are readable but are not writable.
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16 KByte Flash Module (S12FTMRG16K1V1) Offset Module Base + 0x0012 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-23. Flash Reserved6 Register (FRSV6) All bits in the FRSV6 register read 0 and are not writable. 24.3.2.19 Flash Reserved7 Register (FRSV7) This Flash register is reserved for factory testing.
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16 KByte Flash Module (S12FTMRG16K1V1) 24.4 Functional Description 24.4.1 Modes of Operation The FTMRG16K1 module provides the modes of operation normal and special . The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers (see Table 24-25). 24.4.2 IFR Version ID Word The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in Table 24-24. Table 24-24.
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16 KByte Flash Module (S12FTMRG16K1V1) NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash memory due to overstress. Setting FDIV too low can result in incomplete programming or erasure of the Flash memory cells. When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset.
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16 KByte Flash Module (S12FTMRG16K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter
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16 KByte Flash Module (S12FTMRG16K1V1) 24.4.4.3 Valid Flash Module Commands Table 24-25 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 24-25.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-26. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-27. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
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16 KByte Flash Module (S12FTMRG16K1V1) 24.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
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16 KByte Flash Module (S12FTMRG16K1V1) 24.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 24-31. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 24-32 See Table 24-32.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-34. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-36. Read Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 101 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-39.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-41.
PAGE 813
16 KByte Flash Module (S12FTMRG16K1V1) Table 24-44. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 24-45.
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-47.
PAGE 815
16 KByte Flash Module (S12FTMRG16K1V1) 24.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 24-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 24-4).
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16 KByte Flash Module (S12FTMRG16K1V1) Table 24-52. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0D 001 Flash block selection code [1:0]. Table 24-32 See Margin level setting. Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads.
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16 KByte Flash Module (S12FTMRG16K1V1) NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 24.4.6.
PAGE 818
16 KByte Flash Module (S12FTMRG16K1V1) Table 24-57. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 24-25) ACCERR Set if an invalid margin level setting is supplied FSTAT 1 Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 24-32 )1 FPVIOL None MGSTAT1 None MGSTAT0 None As defined by the memory map for FTMRG32K1.
PAGE 819
16 KByte Flash Module (S12FTMRG16K1V1) Table 24-59.
PAGE 820
16 KByte Flash Module (S12FTMRG16K1V1) Table 24-61.
PAGE 821
16 KByte Flash Module (S12FTMRG16K1V1) 24.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 24-64.
PAGE 822
16 KByte Flash Module (S12FTMRG16K1V1) 24.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 24.4.7, “Interrupts”). 24.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 24.5 Security The Flash module provides security information to the MCU.
PAGE 823
16 KByte Flash Module (S12FTMRG16K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 24.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 24.4.6.11 2.
PAGE 824
16 KByte Flash Module (S12FTMRG16K1V1) 8. Reset the MCU 24.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 24-25. 24.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers.
PAGE 825
Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1) Table 25-1. Revision History Revision Number Revision Date V01.04 17 Jun 2010 25.4.6.1/25-860 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] 25.4.6.2/25-861 of the register FSTAT. 25.4.6.3/25-861 25.4.6.14/25-87 1 V01.05 20 aug 2010 25.4.6.2/25-861 Updated description of the commands RD1BLK, MLOADU and MLOADF 25.4.6.12/25-86 8 25.4.6.13/25-87 0 Rev.1.23 31 Jan 2011 25.3.2.
PAGE 826
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
PAGE 827
32 KByte Flash Module (S12FTMRG32K1V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 25.1.2.
PAGE 828
32 KByte Flash Module (S12FTMRG32K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 8Kx39 sector 0 sector 1 Protection sector 63 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 512x22 sector 0 sector 1 sector 255 Figure 25-1. FTMRG32K1 Block Diagram 25.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual, Rev.1.
PAGE 829
32 KByte Flash Module (S12FTMRG32K1V1) 25.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
PAGE 830
32 KByte Flash Module (S12FTMRG32K1V1) The FPROT register, described in Section 25.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection.
PAGE 831
32 KByte Flash Module (S12FTMRG32K1V1) P-Flash START = 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF00 - 0x3_FF0F) Figure 25-2.
PAGE 832
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 25-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 25.4.3 for NVMRES (NVM Resource) detail.
PAGE 833
32 KByte Flash Module (S12FTMRG32K1V1) A summary of the Flash module registers is given in Figure 25-4 with detailed descriptions in the following subsections.
PAGE 834
32 KByte Flash Module (S12FTMRG32K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W = Unimplemented or Reserved Figure 25-4. FTMRG32K1 Register Summary (continued) 25.3.2.
PAGE 835
32 KByte Flash Module (S12FTMRG32K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 25-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed.
PAGE 836
32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 25-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable.
PAGE 837
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 25.5. 25.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 838
32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 25-9.
PAGE 839
32 KByte Flash Module (S12FTMRG32K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DFDIE SFDIE 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 25-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 25-14.
PAGE 840
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 841
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF.
PAGE 842
32 KByte Flash Module (S12FTMRG32K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 25-17.
PAGE 843
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 25-20.
PAGE 844
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x3_8000 0x3_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 32 KByte Flash Module (S12FTMRG32K1V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 25-14.
PAGE 845
32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 25-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 25-21.
PAGE 846
32 KByte Flash Module (S12FTMRG32K1V1) During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 25-4) as indicated by reset condition F in Table 25-23.
PAGE 847
32 KByte Flash Module (S12FTMRG32K1V1) 25.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 25-16.
PAGE 848
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 010 011 100 101 25.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 849
32 KByte Flash Module (S12FTMRG32K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 25.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
PAGE 850
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 25.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-23.
PAGE 851
32 KByte Flash Module (S12FTMRG32K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 25.4 Functional Description 25.4.1 Modes of Operation The FTMRG32K1 module provides the modes of operation normal and special .
PAGE 852
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 25-5. The NVMRES global address map is shown in Table 25-6. 25.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 853
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 25.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 854
32 KByte Flash Module (S12FTMRG32K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter
PAGE 855
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.4.3 Valid Flash Module Commands Table 25-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 25-27.
PAGE 856
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
PAGE 857
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
PAGE 858
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
PAGE 859
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 25-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 25-34 See Table 25-34.
PAGE 860
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 861
32 KByte Flash Module (S12FTMRG32K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 25-39.
PAGE 862
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 25-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 25-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 25.4.6.
PAGE 863
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-43.
PAGE 864
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 25-47.
PAGE 865
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-49.
PAGE 866
32 KByte Flash Module (S12FTMRG32K1V1) user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 25-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 25-52.
PAGE 867
32 KByte Flash Module (S12FTMRG32K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only.
PAGE 868
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 25-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0].
PAGE 869
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-59.
PAGE 870
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-61.
PAGE 871
32 KByte Flash Module (S12FTMRG32K1V1) Table 25-63.
PAGE 872
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 25-66.
PAGE 873
32 KByte Flash Module (S12FTMRG32K1V1) 25.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 25.4.7, “Interrupts”). 25.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 25.5 Security The Flash module provides security information to the MCU.
PAGE 874
32 KByte Flash Module (S12FTMRG32K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 25.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 25.4.6.11 2.
PAGE 875
32 KByte Flash Module (S12FTMRG32K1V1) 8. Reset the MCU 25.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 25-27. 25.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers.
PAGE 876
32 KByte Flash Module (S12FTMRG32K1V1) MC9S12G Family Reference Manual, Rev.1.
PAGE 877
Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1) Table 26-1. Revision History Revision Number Revision Date V01.04 17 Jun 2010 26.4.6.1/26-913 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] 26.4.6.2/26-914 of the register FSTAT. 26.4.6.3/26-914 26.4.6.14/26-92 4 V01.05 20 aug 2010 26.4.6.2/26-914 Updated description of the commands RD1BLK, MLOADU and MLOADF 26.4.6.12/26-92 1 26.4.6.13/26-92 3 Rev.1.23 31 Jan 2011 26.3.2.
PAGE 878
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
PAGE 879
48 KByte Flash Module (S12FTMRG48K1V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 26.1.2.2 • • • • • • 1.
PAGE 880
48 KByte Flash Module (S12FTMRG48K1V1) 26.1.3 Block Diagram The block diagram of the Flash module is shown in Figure 26-1. Figure 26-1. FTMRG48K1 Block Diagram Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 12Kx39 sector 0 sector 1 Protection sector 95 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 768x22 sector 0 sector 1 sector 383 26.
PAGE 881
48 KByte Flash Module (S12FTMRG48K1V1) 26.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
PAGE 882
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x3_4000 – 0x3_FFFF 48 K Description P-Flash Block Contains Flash Configuration Field (see Table 26-4). The FPROT register, described in Section 26.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map.
PAGE 883
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-4. Flash Configuration Field 1 Global Address Size (Bytes) 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 26.4.6.11, “Verify Backdoor Access Key Command,” and Section 26.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 4 Reserved 0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 26.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 26.3.2.
PAGE 884
48 KByte Flash Module (S12FTMRG48K1V1) Figure 26-2.
PAGE 885
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 26-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 26.4.3 for NVMRES (NVM Resource) detail.
PAGE 886
48 KByte Flash Module (S12FTMRG48K1V1) A summary of the Flash module registers is given in Figure 26-4 with detailed descriptions in the following subsections.
PAGE 887
48 KByte Flash Module (S12FTMRG48K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W = Unimplemented or Reserved Figure 26-4. FTMRG48K1 Register Summary (continued) 26.3.2.
PAGE 888
48 KByte Flash Module (S12FTMRG48K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 26-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed.
PAGE 889
48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 26-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable.
PAGE 890
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 26.5. 26.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 891
48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-9.
PAGE 892
48 KByte Flash Module (S12FTMRG48K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DFDIE SFDIE 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 26-14.
PAGE 893
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 894
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF.
PAGE 895
48 KByte Flash Module (S12FTMRG48K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 26-17.
PAGE 896
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 26-20.
PAGE 897
FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 Scenario 0x3_8000 0x3_FFFF Scenario FPHS[1:0] FPLS[1:0] FLASH START FPOPEN = 1 48 KByte Flash Module (S12FTMRG48K1V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 26-14.
PAGE 898
48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 26-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 26-21.
PAGE 899
48 KByte Flash Module (S12FTMRG48K1V1) During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 26-4) as indicated by reset condition F in Table 26-23.
PAGE 900
48 KByte Flash Module (S12FTMRG48K1V1) 26.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 26-16.
PAGE 901
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 010 011 100 101 26.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 902
48 KByte Flash Module (S12FTMRG48K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 26.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
PAGE 903
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 26.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-23.
PAGE 904
48 KByte Flash Module (S12FTMRG48K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 26.4 Functional Description 26.4.1 Modes of Operation The FTMRG48K1 module provides the modes of operation normal and special .
PAGE 905
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 26-5. The NVMRES global address map is shown in Table 26-6. 26.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 906
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 26.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 907
48 KByte Flash Module (S12FTMRG48K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no Read: FSTAT register yes FCCOB Availability Check CCIF Set? yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter
PAGE 908
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.4.3 Valid Flash Module Commands Table 26-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 26-27.
PAGE 909
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
PAGE 910
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
PAGE 911
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
PAGE 912
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 26-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 26-34 See Table 26-34.
PAGE 913
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 914
48 KByte Flash Module (S12FTMRG48K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 26-39.
PAGE 915
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 26-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 26-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 26.4.6.
PAGE 916
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-43.
PAGE 917
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 26-47.
PAGE 918
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-49.
PAGE 919
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 26-52.
PAGE 920
48 KByte Flash Module (S12FTMRG48K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only.
PAGE 921
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 26-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0].
PAGE 922
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-59.
PAGE 923
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-61.
PAGE 924
48 KByte Flash Module (S12FTMRG48K1V1) Table 26-63.
PAGE 925
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 26-66.
PAGE 926
48 KByte Flash Module (S12FTMRG48K1V1) 26.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 26.4.7, “Interrupts”). 26.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 26.5 Security The Flash module provides security information to the MCU.
PAGE 927
48 KByte Flash Module (S12FTMRG48K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 26.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 26.4.6.11 2.
PAGE 928
48 KByte Flash Module (S12FTMRG48K1V1) 8. Reset the MCU 26.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 26-27. 26.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers.
PAGE 929
Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1) Table 27-1. Revision History Revision Number Revision Date V01.04 17 Jun 2010 27.4.6.1/27-964 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] 27.4.6.2/27-965 of the register FSTAT. 27.4.6.3/27-965 27.4.6.14/27-97 5 V01.05 20 aug 2010 27.4.6.2/27-965 Updated description of the commands RD1BLK, MLOADU and MLOADF 27.4.6.12/27-97 2 27.4.6.13/27-97 4 Rev.1.23 31 Jan 2011 27.3.2.
PAGE 930
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
PAGE 931
64 KByte Flash Module (S12FTMRG64K1V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 27.1.2.
PAGE 932
64 KByte Flash Module (S12FTMRG64K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 16Kx39 sector 0 sector 1 Protection sector 127 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 1Kx22 sector 0 sector 1 sector 511 Figure 27-1. FTMRG64K1 Block Diagram 27.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual, Rev.1.
PAGE 933
64 KByte Flash Module (S12FTMRG64K1V1) 27.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
PAGE 934
64 KByte Flash Module (S12FTMRG64K1V1) The FPROT register, described in Section 27.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection.
PAGE 935
64 KByte Flash Module (S12FTMRG64K1V1) P-Flash START = 0x3_0000 Flash Protected/Unprotected Region 32 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes Protection Fixed End 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF0
PAGE 936
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 27-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 27.4.3 for NVMRES (NVM Resource) detail.
PAGE 937
64 KByte Flash Module (S12FTMRG64K1V1) A summary of the Flash module registers is given in Figure 27-4 with detailed descriptions in the following subsections.
PAGE 938
64 KByte Flash Module (S12FTMRG64K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W = Unimplemented or Reserved Figure 27-4. FTMRG64K1 Register Summary (continued) 27.3.2.
PAGE 939
64 KByte Flash Module (S12FTMRG64K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 27-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed.
PAGE 940
64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 27-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable.
PAGE 941
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 27.5. 27.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 942
64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-9.
PAGE 943
64 KByte Flash Module (S12FTMRG64K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DFDIE SFDIE 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 27-14.
PAGE 944
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 945
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF.
PAGE 946
64 KByte Flash Module (S12FTMRG64K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 27-17.
PAGE 947
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 27-20.
PAGE 948
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x3_8000 0x3_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 64 KByte Flash Module (S12FTMRG64K1V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 27-14.
PAGE 949
64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 27-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 27-21.
PAGE 950
64 KByte Flash Module (S12FTMRG64K1V1) During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 27-4) as indicated by reset condition F in Table 27-23.
PAGE 951
64 KByte Flash Module (S12FTMRG64K1V1) 27.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 27-16.
PAGE 952
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 010 011 100 101 27.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 953
64 KByte Flash Module (S12FTMRG64K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 27.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
PAGE 954
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 27.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-23.
PAGE 955
64 KByte Flash Module (S12FTMRG64K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 27.4 Functional Description 27.4.1 Modes of Operation The FTMRG64K1 module provides the modes of operation normal and special .
PAGE 956
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 27-5. The NVMRES global address map is shown in Table 27-6. 27.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 957
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 27.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 958
64 KByte Flash Module (S12FTMRG64K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter
PAGE 959
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.4.3 Valid Flash Module Commands Table 27-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 27-27.
PAGE 960
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
PAGE 961
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
PAGE 962
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
PAGE 963
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 27-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 27-34 See Table 27-34.
PAGE 964
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 965
64 KByte Flash Module (S12FTMRG64K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 27-39.
PAGE 966
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 27-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 27-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 27.4.6.
PAGE 967
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-43.
PAGE 968
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 27-47.
PAGE 969
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-49.
PAGE 970
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 27-52.
PAGE 971
64 KByte Flash Module (S12FTMRG64K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads. It is not possible to apply user margin levels to the P-Flash block only.
PAGE 972
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 27-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0].
PAGE 973
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-59.
PAGE 974
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-61.
PAGE 975
64 KByte Flash Module (S12FTMRG64K1V1) Table 27-63.
PAGE 976
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 27-66.
PAGE 977
64 KByte Flash Module (S12FTMRG64K1V1) 27.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 27.4.7, “Interrupts”). 27.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 27.5 Security The Flash module provides security information to the MCU.
PAGE 978
64 KByte Flash Module (S12FTMRG64K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 27.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 27.4.6.11 2.
PAGE 979
64 KByte Flash Module (S12FTMRG64K1V1) 8. Reset the MCU 27.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 27-27. 27.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers.
PAGE 980
64 KByte Flash Module (S12FTMRG64K1V1) MC9S12G Family Reference Manual, Rev.1.
PAGE 981
Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1) Table 28-1. Revision History Revision Number Revision Date V01.04 17 Jun 2010 28.4.6.1/28-101 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] of the register FSTAT. 6 28.4.6.2/28-101 7 28.4.6.3/28-101 8 28.4.6.14/28-10 27 V01.05 20 aug 2010 28.4.6.2/28-101 Updated description of the commands RD1BLK, MLOADU and MLOADF 7 28.4.6.12/28-10 24 28.4.6.13/28-10 26 Rev.1.23 31 Jan 2011 28.3.2.
PAGE 982
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
PAGE 983
96 KByte Flash Module (S12FTMRG96K1V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 28.1.2.
PAGE 984
96 KByte Flash Module (S12FTMRG96K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 24Kx39 sector 0 sector 1 Protection sector 191 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 1.5Kx22 sector 0 sector 1 sector 767 Figure 28-1. FTMRG96K1 Block Diagram 28.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual, Rev.1.
PAGE 985
96 KByte Flash Module (S12FTMRG96K1V1) 28.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
PAGE 986
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x2_8000 – 0x3_FFFF 96 K Description P-Flash Block Contains Flash Configuration Field (see Table 28-4) The FPROT register, described in Section 28.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase.
PAGE 987
96 KByte Flash Module (S12FTMRG96K1V1) P-Flash START = 0x2_8000 Flash Protected/Unprotected Region 64 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_FF
PAGE 988
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 28-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF 1 Description Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved NVMRES - See Section 28.4.3 for NVMRES (NVM Resource) detail.
PAGE 989
96 KByte Flash Module (S12FTMRG96K1V1) A summary of the Flash module registers is given in Figure 28-4 with detailed descriptions in the following subsections.
PAGE 990
96 KByte Flash Module (S12FTMRG96K1V1) Address & Name 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W R W R W R W R W = Unimplemented or Reserved Figure 28-4. FTMRG96K1 Register Summary (continued) 28.3.2.
PAGE 991
96 KByte Flash Module (S12FTMRG96K1V1) CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). Table 28-7. FCLKDIV Field Descriptions Field 7 FDIVLD Description Clock Divider Loaded 0 FCLKDIV register has not been written since the last reset 1 FCLKDIV register has been written since the last reset 6 FDIVLCK Clock Divider Locked 0 FDIV field is open for writing 1 FDIV value is locked and cannot be changed.
PAGE 992
96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 28-6. Flash Security Register (FSEC) 1 Loaded from IFR Flash configuration field, during reset sequence. All bits in the FSEC register are readable but not writable.
PAGE 993
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-11. Flash Security States 1 SEC[1:0] Status of Security 00 SECURED 01 SECURED1 10 UNSECURED 11 SECURED Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 28.5. 28.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 994
96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU. Offset Module Base + 0x0004 7 R 6 5 0 0 CCIE 4 3 2 0 0 IGNSF 1 0 FDFD FSFD 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-9.
PAGE 995
96 KByte Flash Module (S12FTMRG96K1V1) Offset Module Base + 0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 1 0 DFDIE SFDIE 0 0 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-10. Flash Error Configuration Register (FERCNFG) All assigned bits in the FERCNFG register are readable and writable. Table 28-14.
PAGE 996
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-15. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 997
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-16. FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash command operation.1 The DFDIF flag is cleared by writing a 1 to DFDIF.
PAGE 998
96 KByte Flash Module (S12FTMRG96K1V1) Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the same P-Flash block are protected. Table 28-17.
PAGE 999
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-19. P-Flash Protection Higher Address Range FPHS[1:0] Global Address Range Protected Size 00 0x3_F800–0x3_FFFF 2 Kbytes 01 0x3_F000–0x3_FFFF 4 Kbytes 10 0x3_E000–0x3_FFFF 8 Kbytes 11 0x3_C000–0x3_FFFF 16 Kbytes Table 28-20.
PAGE 1000
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x3_8000 0x3_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 96 KByte Flash Module (S12FTMRG96K1V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 28-14.
PAGE 1001
96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 28-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 28-21.
PAGE 1002
96 KByte Flash Module (S12FTMRG96K1V1) P-Flash memory (see Table 28-4) as indicated by reset condition F in Table 28-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed.
PAGE 1003
96 KByte Flash Module (S12FTMRG96K1V1) 28.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 28-16.
PAGE 1004
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 010 011 100 101 28.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 1005
96 KByte Flash Module (S12FTMRG96K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 28.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
PAGE 1006
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 28.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-23.
PAGE 1007
96 KByte Flash Module (S12FTMRG96K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 28.4 Functional Description 28.4.1 Modes of Operation The FTMRG96K1 module provides the modes of operation normal and special .
PAGE 1008
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 28-5. The NVMRES global address map is shown in Table 28-6. 28.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 1009
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 28.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 1010
96 KByte Flash Module (S12FTMRG96K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter
PAGE 1011
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.4.3 Valid Flash Module Commands Table 28-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 28-27.
PAGE 1012
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
PAGE 1013
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
PAGE 1014
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
PAGE 1015
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 28-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 28-34 See Table 28-34.
PAGE 1016
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.3 Erase Verify P-Flash Section Command The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. Table 28-36.
PAGE 1017
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-38. Read Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed.
PAGE 1018
96 KByte Flash Module (S12FTMRG96K1V1) 1 Global address [2:0] must be 000 Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The CCIF flag will set after the Program P-Flash operation has completed. Table 28-41.
PAGE 1019
96 KByte Flash Module (S12FTMRG96K1V1) The reserved nonvolatile information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash will return invalid data. Table 28-43.
PAGE 1020
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.8 Erase Flash Block Command The Erase Flash Block operation will erase all addresses in a P-Flash or EEPROM block. Table 28-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased.
PAGE 1021
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-49.
PAGE 1022
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.6.11 Verify Backdoor Access Key Command The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the FSEC register (see Table 28-10). The Verify Backdoor Access Key command releases security if user-supplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 28-4).
PAGE 1023
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-54. Set User Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0D 001 Flash block selection code [1:0]. Table 28-34 See Margin level setting. Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads.
PAGE 1024
96 KByte Flash Module (S12FTMRG96K1V1) NOTE User margin levels can be used to check that Flash memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking Flash memory contents at user margin levels, a potential loss of information has been detected. 28.4.6.
PAGE 1025
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-59. Set Field Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 28-27) ACCERR Set if an invalid margin level setting is supplied FSTAT 1 Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 28-34 )1 FPVIOL None MGSTAT1 None MGSTAT0 None As defined by the memory map for FTMRG96K1.
PAGE 1026
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-61.
PAGE 1027
96 KByte Flash Module (S12FTMRG96K1V1) Table 28-63.
PAGE 1028
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 28-66.
PAGE 1029
96 KByte Flash Module (S12FTMRG96K1V1) 28.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 28.4.7, “Interrupts”). 28.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 28.5 Security The Flash module provides security information to the MCU.
PAGE 1030
96 KByte Flash Module (S12FTMRG96K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 28.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 28.4.6.11 2.
PAGE 1031
96 KByte Flash Module (S12FTMRG96K1V1) 8. Reset the MCU 28.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 28-27. 28.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers.
PAGE 1032
96 KByte Flash Module (S12FTMRG96K1V1) MC9S12G Family Reference Manual, Rev.1.
PAGE 1033
Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1) Table 29-1. Revision History Revision Number Revision Date V01.11 17 Jun 2010 29.4.6.1/29-106 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] of the register FSTAT. 8 29.4.6.2/29-106 9 29.4.6.3/29-106 9 29.4.6.14/29-10 79 V01.12 31 aug 2010 29.4.6.2/29-106 Updated description of the commands RD1BLK, MLOADU and MLOADF 9 29.4.6.12/29-10 76 29.4.6.13/29-10 78 Rev.1.23 31 Jan 2011 29.3.2.
PAGE 1034
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
PAGE 1035
128 KByte Flash Module (S12FTMRG128K1V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 29.1.2.
PAGE 1036
128 KByte Flash Module (S12FTMRG128K1V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 32Kx39 sector 0 sector 1 Protection sector 255 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 2Kx22 sector 0 sector 1 sector 1023 Figure 29-1. FTMRG128K1 Block Diagram 29.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual, Rev.1.
PAGE 1037
128 KByte Flash Module (S12FTMRG128K1V1) 29.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
PAGE 1038
128 KByte Flash Module (S12FTMRG128K1V1) The FPROT register, described in Section 29.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x3_8000 in the Flash memory (called the lower region), one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection.
PAGE 1039
128 KByte Flash Module (S12FTMRG128K1V1) P-Flash START = 0x2_0000 Flash Protected/Unprotected Region 96 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3_
PAGE 1040
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 29.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 29.4.2 Table 29-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 29-5) 0x0_4100 – 0x0_41FF 256 Reserved.
PAGE 1041
128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 29.3). A summary of the Flash module registers is given in Figure 29-4 with detailed descriptions in the following subsections.
PAGE 1042
128 KByte Flash Module (S12FTMRG128K1V1) Address & Name 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 7 6 5 4 3 2 1 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PAGE 1043
128 KByte Flash Module (S12FTMRG128K1V1) Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIVLCK FDIV[5:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 29-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable.
PAGE 1044
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 29.3.2.2 MIN1 MAX2 1.0 1.6 1.6 BUSCLK Frequency (MHz) FDIV[5:0] FDIV[5:0] 1 MAX 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.
PAGE 1045
128 KByte Flash Module (S12FTMRG128K1V1) indicated by reset condition F in Figure 29-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 29-9.
PAGE 1046
128 KByte Flash Module (S12FTMRG128K1V1) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 29-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 29.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 29.3.2.
PAGE 1047
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 29.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 29.3.2.8).
PAGE 1048
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 29.3.2.
PAGE 1049
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-15. FSTAT Field Descriptions (continued) Field 3 MGBUSY 2 RSVD Description Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0.
PAGE 1050
128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 29-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence.
PAGE 1051
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-17. FPROT Field Descriptions (continued) Field Description 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000.
PAGE 1052
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x3_8000 0x3_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 128 KByte Flash Module (S12FTMRG128K1V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 29-14.
PAGE 1053
128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 29-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 29-21.
PAGE 1054
128 KByte Flash Module (S12FTMRG128K1V1) P-Flash memory (see Table 29-4) as indicated by reset condition F in Table 29-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed.
PAGE 1055
128 KByte Flash Module (S12FTMRG128K1V1) 29.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 29-16.
PAGE 1056
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 010 011 100 101 29.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 1057
128 KByte Flash Module (S12FTMRG128K1V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 29.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
PAGE 1058
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 29.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-23.
PAGE 1059
128 KByte Flash Module (S12FTMRG128K1V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 29.4 Functional Description 29.4.1 Modes of Operation The FTMRG128K1 module provides the modes of operation normal and special .
PAGE 1060
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 29-5. The NVMRES global address map is shown in Table 29-6. 29.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 1061
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 29.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 1062
128 KByte Flash Module (S12FTMRG128K1V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command paramet
PAGE 1063
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.4.3 Valid Flash Module Commands Table 29-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 29-27.
PAGE 1064
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
PAGE 1065
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
PAGE 1066
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
PAGE 1067
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0] bits determine which block must be verified. Table 29-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 29-34 See Table 29-34.
PAGE 1068
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 1069
128 KByte Flash Module (S12FTMRG128K1V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 29-39.
PAGE 1070
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 29-27) ACCERR Set if an invalid global address [17:0] is supplied (see Table 29-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 29.4.6.
PAGE 1071
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-43.
PAGE 1072
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 29-47.
PAGE 1073
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-49.
PAGE 1074
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 29-52.
PAGE 1075
128 KByte Flash Module (S12FTMRG128K1V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads.
PAGE 1076
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.6.13 Set Field Margin Level Command The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set the margin level specified for future read operations of the P-Flash or EEPROM block. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the Table 29-57.
PAGE 1077
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-59.
PAGE 1078
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-61.
PAGE 1079
128 KByte Flash Module (S12FTMRG128K1V1) Table 29-63.
PAGE 1080
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.7 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an ECC fault. Table 29-66.
PAGE 1081
128 KByte Flash Module (S12FTMRG128K1V1) 29.4.8 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 29.4.7, “Interrupts”). 29.4.9 Stop Mode If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation will be completed before the MCU is allowed to enter stop mode. 29.5 Security The Flash module provides security information to the MCU.
PAGE 1082
128 KByte Flash Module (S12FTMRG128K1V1) The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 29.3.2.2), the MCU can be unsecured by the backdoor key access sequence described below: 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Section 29.4.6.11 2.
PAGE 1083
128 KByte Flash Module (S12FTMRG128K1V1) 8. Reset the MCU 29.5.3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU operating mode and security state as shown in Table 29-27. 29.6 Initialization On each system reset the flash module executes an initialization sequence which establishes initial values for the Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and FSEC registers.
PAGE 1084
128 KByte Flash Module (S12FTMRG128K1V1) MC9S12G Family Reference Manual, Rev.1.
PAGE 1085
Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1) Table 30-1. Revision History Revision Number Revision Date V01.06 23 Jun 2010 30.4.6.2/30-112 Updated description of the commands RD1BLK, MLOADU and MLOADF 1 30.4.6.12/30-11 28 30.4.6.13/30-11 29 V01.07 20 aug 2010 30.4.6.2/30-112 Updated description of the commands RD1BLK, MLOADU and MLOADF 1 30.4.6.12/30-11 28 30.4.6.13/30-11 29 Rev.1.23 31 Jan 2011 30.3.2.9/30-110 Updated description of protection on Section 30.3.2.9 4 30.
PAGE 1086
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
PAGE 1087
192 KByte Flash Module (S12FTMRG192K2V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 30.1.2.
PAGE 1088
192 KByte Flash Module (S12FTMRG192K2V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 48Kx39 sector 0 sector 1 Protection sector 383 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 2Kx22 sector 0 sector 1 sector 1023 Figure 30-1. FTMRG192K2 Block Diagram 30.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual, Rev.1.
PAGE 1089
192 KByte Flash Module (S12FTMRG192K2V1) 30.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
PAGE 1090
192 KByte Flash Module (S12FTMRG192K2V1) Table 30-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x1_0000 – 0x3_FFFF 192 K Description P-Flash Block Contains Flash Configuration Field (see Table 30-4). The FPROT register, described in Section 30.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map.
PAGE 1091
192 KByte Flash Module (S12FTMRG192K2V1) P-Flash START = 0x1_0000 Flash Protected/Unprotected Region 160 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3
PAGE 1092
192 KByte Flash Module (S12FTMRG192K2V1) Table 30-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 30.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 30.4.2 Table 30-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 30-5) 0x0_4100 – 0x0_41FF 256 Reserved.
PAGE 1093
192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 30.3). A summary of the Flash module registers is given in Figure 30-4 with detailed descriptions in the following subsections.
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192 KByte Flash Module (S12FTMRG192K2V1) Address & Name 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 7 6 5 4 3 2 1 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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192 KByte Flash Module (S12FTMRG192K2V1) Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIVLCK FDIV[5:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 30-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 30.3.2.2 MIN1 MAX2 1.0 1.6 1.6 BUSCLK Frequency (MHz) FDIV[5:0] FDIV[5:0] 1 MAX 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.
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192 KByte Flash Module (S12FTMRG192K2V1) indicated by reset condition F in Figure 30-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 30-9.
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192 KByte Flash Module (S12FTMRG192K2V1) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 30-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 30.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 30.3.2.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 30.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 30.3.2.8).
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 30.3.2.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-15. FSTAT Field Descriptions (continued) Field 3 MGBUSY 2 RSVD Description Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 30-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-17. FPROT Field Descriptions (continued) Field Description 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000.
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FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x3_8000 0x3_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 192 KByte Flash Module (S12FTMRG192K2V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 30-14.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 30-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 30-21.
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192 KByte Flash Module (S12FTMRG192K2V1) P-Flash memory (see Table 30-4) as indicated by reset condition F in Table 30-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 30-16.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 010 011 100 101 30.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
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192 KByte Flash Module (S12FTMRG192K2V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 30.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 30.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-23.
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192 KByte Flash Module (S12FTMRG192K2V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 30-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 30.4 Functional Description 30.4.1 Modes of Operation The FTMRG192K2 module provides the modes of operation normal and special .
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192 KByte Flash Module (S12FTMRG192K2V1) 30.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 30-5. The NVMRES global address map is shown in Table 30-6. 30.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 30.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
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192 KByte Flash Module (S12FTMRG192K2V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command paramet
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192 KByte Flash Module (S12FTMRG192K2V1) 30.4.4.3 Valid Flash Module Commands Table 30-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 30-27.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0]bits determine which block must be verified. Table 30-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 30-34 See Table 30-34.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
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192 KByte Flash Module (S12FTMRG192K2V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 30-39.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 30-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 30-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 30.4.6.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-43.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 30-47.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-49.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 30-52.
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192 KByte Flash Module (S12FTMRG192K2V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 30-34 See Margin level setting. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads.
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192 KByte Flash Module (S12FTMRG192K2V1) CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 30.4.6.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 30-62.
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192 KByte Flash Module (S12FTMRG192K2V1) Table 30-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 001 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 30.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased.
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192 KByte Flash Module (S12FTMRG192K2V1) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 30.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request.
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192 KByte Flash Module (S12FTMRG192K2V1) 30.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 30-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F.
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192 KByte Flash Module (S12FTMRG192K2V1) reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 30.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2.
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192 KByte Flash Module (S12FTMRG192K2V1) If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual, Rev.1.
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192 KByte Flash Module (S12FTMRG192K2V1) MC9S12G Family Reference Manual, Rev.1.
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Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1) Table 31-1. Revision History Revision Number Revision Date V01.06 23 Jun 2010 31.4.6.2/31-117 Updated description of the commands RD1BLK, MLOADU and MLOADF 3 31.4.6.12/31-11 80 31.4.6.13/31-11 81 V01.07 20 aug 2010 31.4.6.2/31-117 Updated description of the commands RD1BLK, MLOADU and MLOADF 3 31.4.6.12/31-11 80 31.4.6.13/31-11 81 Rev.1.23 31 Jan 2011 31.3.2.9/31-115 Updated description of protection on Section 31.3.2.9 6 31.
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The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
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240 KByte Flash Module (S12FTMRG240K2V1) • • • • • Single bit fault correction and double bit fault detection within a 32-bit double word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and phrase program operation Ability to read the P-Flash memory while programming a word in the EEPROM memory Flexible protection scheme to prevent accidental program or erase of P-Flash memory 31.1.2.
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240 KByte Flash Module (S12FTMRG240K2V1) Flash Interface Command Interrupt Request Error Interrupt Request 16bit internal bus Registers P-Flash 60Kx39 sector 0 sector 1 Protection sector 479 Security Bus Clock Clock Divider FCLK Memory Controller CPU EEPROM 2Kx22 sector 0 sector 1 sector 1023 Figure 31-1. FTMRG240K2 Block Diagram 31.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12G Family Reference Manual, Rev.1.
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240 KByte Flash Module (S12FTMRG240K2V1) 31.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of flag CCIF reads as ’0’) is not allowed.
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240 KByte Flash Module (S12FTMRG240K2V1) Table 31-3. P-Flash Memory Addressing Global Address Size (Bytes) 0x0_4000 – 0x3_FFFF 240 K Description P-Flash Block Contains Flash Configuration Field (see Table 31-4). The FPROT register, described in Section 31.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map.
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240 KByte Flash Module (S12FTMRG240K2V1) P-Flash START = 0x0_4000 Flash Protected/Unprotected Region 208 Kbytes 0x3_8000 0x3_8400 0x3_8800 0x3_9000 Protection Fixed End Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x3_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) Protection Movable End 0x3_C000 Protection Fixed End 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x3_F000 0x3_F800 P-Flash END = 0x3_FFFF Flash Configuration Field 16 bytes (0x3
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240 KByte Flash Module (S12FTMRG240K2V1) Table 31-5. Program IFR Fields 1 Global Address Size (Bytes) 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 31.4.6.6, “Program Once Command” Field Description Used to track firmware patch versions, see Section 31.4.2 Table 31-6. Memory Controller Resource Fields (NVMRES1=1) Global Address Size (Bytes) 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 31-5) 0x0_4100 – 0x0_41FF 256 Reserved.
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240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2 Register Descriptions The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 31.3). A summary of the Flash module registers is given in Figure 31-4 with detailed descriptions in the following subsections.
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240 KByte Flash Module (S12FTMRG240K2V1) Address & Name 0x000A FCCOBHI 0x000B FCCOBLO 0x000C FRSV1 0x000D FRSV2 0x000E FRSV3 0x000F FRSV4 0x0010 FOPT 0x0011 FRSV5 0x0012 FRSV6 0x0013 FRSV7 7 6 5 4 3 2 1 0 CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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240 KByte Flash Module (S12FTMRG240K2V1) Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIVLCK FDIV[5:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 31-5. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable.
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240 KByte Flash Module (S12FTMRG240K2V1) Table 31-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) 1 2 31.3.2.2 MIN1 MAX2 1.0 1.6 1.6 BUSCLK Frequency (MHz) FDIV[5:0] FDIV[5:0] 1 MAX 0x00 16.6 17.6 0x10 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.
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240 KByte Flash Module (S12FTMRG240K2V1) indicated by reset condition F in Figure 31-6. If a double bit fault is detected while reading the P-Flash phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set to leave the Flash module in a secured state with backdoor key access disabled. Table 31-9.
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240 KByte Flash Module (S12FTMRG240K2V1) CCOBIX bits are readable and writable while remaining bits read 0 and are not writable. Table 31-12. FCCOBIX Field Descriptions Field Description 2–0 CCOBIX[1:0] Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to. See 31.3.2.11 Flash Common Command Object Register (FCCOB),” for more details. 31.3.2.
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240 KByte Flash Module (S12FTMRG240K2V1) Table 31-13. FCNFG Field Descriptions Field Description 7 CCIE Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command has completed. 0 Command complete interrupt disabled 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 31.3.2.7) 4 IGNSF Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see Section 31.3.2.8).
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240 KByte Flash Module (S12FTMRG240K2V1) Table 31-14. FERCNFG Field Descriptions Field Description 1 DFDIE Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation. 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set (see Section 31.3.2.
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240 KByte Flash Module (S12FTMRG240K2V1) Table 31-15. FSTAT Field Descriptions (continued) Field 3 MGBUSY 2 RSVD Description Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller. 0 Memory Controller is idle 1 Memory Controller is busy executing a Flash command (CCIF = 0) Reserved Bit — This bit is reserved and always reads 0.
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240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2.9 P-Flash Protection Register (FPROT) The FPROT register defines which P-Flash sectors are protected against program and erase operations. Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F1 F1 F1 F1 F1 F1 F1 F1 = Unimplemented or Reserved Figure 31-13. Flash Protection Register (FPROT) 1 Loaded from IFR Flash configuration field, during reset sequence.
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240 KByte Flash Module (S12FTMRG240K2V1) Table 31-17. FPROT Field Descriptions (continued) Field Description 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000.
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FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x3_8000 0x3_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 240 KByte Flash Module (S12FTMRG240K2V1) FPHS[1:0] 0x3_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x3_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 31-14.
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240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 31-21 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 31-21.
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240 KByte Flash Module (S12FTMRG240K2V1) P-Flash memory (see Table 31-4) as indicated by reset condition F in Table 31-23. To change the EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed.
PAGE 1159
240 KByte Flash Module (S12FTMRG240K2V1) 31.3.2.11 Flash Common Command Object Register (FCCOB) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte wide reads and writes are allowed to the FCCOB register. Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 31-16.
PAGE 1160
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-24. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 0 [15:8] LO Data 0 [7:0] HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 010 011 100 101 31.3.2.12 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 1161
240 KByte Flash Module (S12FTMRG240K2V1) Offset Module Base + 0x000E R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-20. Flash Reserved3 Register (FRSV3) All bits in the FRSV3 register read 0 and are not writable. 31.3.2.15 Flash Reserved4 Register (FRSV4) This Flash register is reserved for factory testing.
PAGE 1162
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-25. FOPT Field Descriptions Field Description 7–0 NV[7:0] Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV bits. 31.3.2.17 Flash Reserved5 Register (FRSV5) This Flash register is reserved for factory testing. Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-23.
PAGE 1163
240 KByte Flash Module (S12FTMRG240K2V1) Offset Module Base + 0x0013 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 31-25. Flash Reserved7 Register (FRSV7) All bits in the FRSV7 register read 0 and are not writable. 31.4 Functional Description 31.4.1 Modes of Operation The FTMRG240K2 module provides the modes of operation normal and special .
PAGE 1164
240 KByte Flash Module (S12FTMRG240K2V1) 31.4.3 Internal NVM resource (NVMRES) IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown in Table 31-5. The NVMRES global address map is shown in Table 31-6. For FTMRG240K2 the NVMRES address area is shared with 16K space of P-Flash area, as shown in Figure 31-2. 31.4.4 Flash Command Operations Flash command operations are used to modify Flash memory contents.
PAGE 1165
240 KByte Flash Module (S12FTMRG240K2V1) 31.4.4.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 31.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 1166
240 KByte Flash Module (S12FTMRG240K2V1) START Read: FCLKDIV register Clock Divider Value Check FDIV Correct? no no yes FCCOB Availability Check CCIF Set? Read: FSTAT register yes Read: FSTAT register Note: FCLKDIV must be set after each reset Write: FCLKDIV register no CCIF Set? yes Results from previous Command ACCERR/ FPVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command paramet
PAGE 1167
240 KByte Flash Module (S12FTMRG240K2V1) 31.4.4.3 Valid Flash Module Commands Table 31-27 present the valid Flash commands, as enabled by the combination of the functional MCU mode (Normal SingleChip NS, Special Singlechip SS) with the MCU security state (Unsecured, Secured). Special Singlechip mode is selected by input mmc_ss_mode_ts2 asserted. MCU Secured state is selected by input mmc_secure input asserted. + Table 31-27.
PAGE 1168
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-28. P-Flash Commands FCMD Command 0x02 Erase Verify Block 0x03 Erase Verify P-Flash Section 0x04 Read Once 0x06 Program P-Flash 0x07 Program Once Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block that is allowed to be programmed only once. 0x08 Erase All Blocks Erase all P-Flash (and EEPROM) blocks.
PAGE 1169
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-29. EEPROM Commands FCMD Command Function on EEPROM Memory 0x08 Erase All Blocks Erase all EEPROM (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the DPOPEN bit in the EEPROT register are set prior to launching the command. 0x09 Erase Flash Block Erase a EEPROM (or P-Flash) block.
PAGE 1170
240 KByte Flash Module (S12FTMRG240K2V1) 31.4.6 Flash Command Description This section provides details of all available Flash commands launched by a command write sequence.
PAGE 1171
240 KByte Flash Module (S12FTMRG240K2V1) 31.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB FlashBlockSelectionCode[1:0]bits determine which block must be verified. Table 31-33. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Flash block selection code [1:0]. Table 31-34 See Table 31-34.
PAGE 1172
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-36. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased.
PAGE 1173
240 KByte Flash Module (S12FTMRG240K2V1) Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. 8 Table 31-39.
PAGE 1174
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-41. Program P-Flash Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 101 at command launch Set if command not available in current mode (see Table 31-27) ACCERR Set if an invalid global address [17:0] is supplied see Table 31-3) Set if a misaligned phrase address is supplied (global address [2:0] != 000) FSTAT FPVIOL 31.4.6.
PAGE 1175
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-43.
PAGE 1176
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-46. Erase Flash Block Command FCCOB Requirements CCOBIX[2:0] 000 001 FCCOB Parameters Global address [17:16] to identify Flash block 0x09 Global address [15:0] in Flash block to be erased Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block operation has completed. Table 31-47.
PAGE 1177
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-49.
PAGE 1178
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-4). The Verify Backdoor Access Key command must not be executed from the Flash block containing the backdoor comparison key to avoid code runaway. Table 31-52.
PAGE 1179
240 KByte Flash Module (S12FTMRG240K2V1) Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the user margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the P-Flash block is targeted, the P-Flash user margin levels are applied to both P-Flash and EEPROM reads.
PAGE 1180
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-57. Set Field Margin Level Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0E 001 Flash block selection code [1:0]. Table 31-34 See Margin level setting. Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. NOTE When the EEPROM block is targeted, the EEPROM field margin levels are applied only to the EEPROM reads.
PAGE 1181
240 KByte Flash Module (S12FTMRG240K2V1) CAUTION Field margin levels must only be used during verify of the initial factory programming. NOTE Field margin levels can be used to check that Flash memory contents have adequate margin for data retention at the normal level setting. If unexpected results are encountered when checking Flash memory contents at field margin levels, the Flash memory contents should be erased and reprogrammed. 31.4.6.
PAGE 1182
240 KByte Flash Module (S12FTMRG240K2V1) 31.4.6.15 Program EEPROM Command The Program EEPROM operation programs one to four previously erased words in the EEPROM block. The Program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Table 31-62.
PAGE 1183
240 KByte Flash Module (S12FTMRG240K2V1) Table 31-64. Erase EEPROM Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 001 0x12 Global address [17:16] to identify EEPROM block Global address [15:0] anywhere within the sector to be erased. See Section 31.1.2.2 for EEPROM sector size. Upon clearing CCIF to launch the Erase EEPROM Sector command, the Memory Controller will erase the selected Flash sector and verify that it is erased.
PAGE 1184
240 KByte Flash Module (S12FTMRG240K2V1) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 31.4.7.1 Description of Flash Interrupt Operation The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request.
PAGE 1185
240 KByte Flash Module (S12FTMRG240K2V1) 31.5 Security The Flash module provides security information to the MCU. The Flash security state is defined by the SEC bits of the FSEC register (see Table 31-11). During reset, the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F.
PAGE 1186
240 KByte Flash Module (S12FTMRG240K2V1) reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration field. 31.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM A secured MCU can be unsecured in special single chip mode by using the following method to erase the P-Flash and EEPROM memory: 1. Reset the MCU into special single chip mode 2.
PAGE 1187
240 KByte Flash Module (S12FTMRG240K2V1) If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. MC9S12G Family Reference Manual, Rev.1.
PAGE 1188
240 KByte Flash Module (S12FTMRG240K2V1) MC9S12G Family Reference Manual, Rev.1.
PAGE 1189
Appendix A Electrical Characteristics Revision History Version Number Revision Date Rev 0.37 24-Apr-2012 • Added Figure A-2 Rev 0.38 16-Aug-2012 • Updated Table A-18 (Num 1 12) • Updated Table A-43 (Num 9) • Corrected Section A.3.1, “Measurement Conditions” Rev 0.39 13-Sep-2012 • Added Section A.4.2.1, “Differential Reference Voltage” • Updated Table A-43 (Num 9) Rev 0.40 14-Sep-2012 • Updated Table A-43 (Num 9) • Updated Table A-19 (Num 5,6) Rev 0.41 26-Oct-2012 • • • • • Rev 0.
PAGE 1190
Electrical Characteristics Version Number Revision Date Rev 0.45 9-Jan-2013 • • • • • • • • Rev 0.46 24-Jan-2013 • Updated Table A-16 (Num 1-3) • Updated Table A-17 (Num 4, 8) • Added Table A-44 (Num 1-3) Rev 0.47 25-Jan-2013 • Updated Table A-29 (Num 5, 6) • Added Table A-38 A.
PAGE 1191
Electrical Characteristics The VDDF, VSS1 pin pair supplies the internal NVM logic. All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal. VDDA, VDDX and VSSA, VSSX are connected by diodes for ESD protection. NOTE In the following context VDD35 is used for either VDDA, VDDR, and VDDX; VSS35 is used for either VSSA and VSSX unless otherwise noted. IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. A.1.
PAGE 1192
Electrical Characteristics A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.
PAGE 1193
Electrical Characteristics Table A-2. ESD and Latch-up Test Conditions Model Description Human Body Symbol Value Unit Series Resistance R1 1500 Ω Storage Capacitance C 100 pF Number of Pulse per pin positive negative - 3 3 Symbol Min Max Unit Table A-3. ESD and Latch-Up Protection Characteristics Num C 1 C Human Body Model (HBM) VHBM 2000 - V 2 C Charge Device Model (CDM) VCDM 500 - V 3 C Charge Device Model (CDM) (Corner Pins) VCDM 750 - V A.1.
PAGE 1194
Electrical Characteristics 1 Please refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more details about the relation between ambient temperature TA and device junction temperature TJ. NOTE Operation is guaranteed when powering down until low voltage reset assertion. MC9S12G Family Reference Manual, Rev.1.
PAGE 1195
Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded.
PAGE 1196
Electrical Characteristics MC9S12G Family Reference Manual, Rev.1.
PAGE 1197
Electrical Characteristics Table A-5.
PAGE 1198
Electrical Characteristics Table A-5.
PAGE 1199
Electrical Characteristics 1 The values for thermal resistance are achieved by package simulations Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.J Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. .Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured in simulation on the top surface of the board near the package.
PAGE 1200
Electrical Characteristics Table A-7. 3.3-V I/O Characteristics (Junction Temperature From +150°C To +160°C) Conditions are 3.15 V < VDD35 < 3.6 V junction temperature from +150°C to +160°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min Typ Max Unit 1 C Input high voltage VIH 0.65*VDD35 — — V 2 T Input high voltage VIH — — VDD35+0.3 V 3 C Input low voltage VIL — — 0.
PAGE 1201
Electrical Characteristics Table A-8. 5-V I/O Characteristics (Junction Temperature From –40°C To +150°C) Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min Typ Max Unit 0.65*VDD35 — — V 1 P Input high voltage V 2 T Input high voltage VIH — — VDD35+0.3 V 3 P Input low voltage VIL — — 0.
PAGE 1202
Electrical Characteristics Table A-9. 5-V I/O Characteristics (Junction Temperature From +150°C To +160°C) Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from +150°C to +160°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min Typ Max Unit 0.65*VDD35 — — V 1 C Input high voltage V 2 T Input high voltage VIH — — VDD35+0.3 V 3 C Input low voltage VIL — — 0.
PAGE 1203
Electrical Characteristics Table A-11. Pin Interrupt Characteristics (Junction Temperature From +150°C To +160°C) Conditions are 3.13V < VDD35 < 5.5 V unless otherwise noted.
PAGE 1204
Electrical Characteristics Table A-12. CPMU Configuration for Pseudo Stop Current Measurement CPMU REGISTER Bit settings/Conditions CPMURTI RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111; CPMUCOP WCOP=1, CR[2:0]=111 Table A-13.
PAGE 1205
Electrical Characteristics Table A-14. Peripheral Configurations for Run & Wait Current Measurement Peripheral Configuration TIM The peripheral shall be configured to output compare mode, pulse accumulator and modulus counter enabled. COP & RTI ACMP1 Both modules are enabled. The module is enabled with analog output on. The ACMPP and ACMPM are toggling with 0-1 and 1-0. DAC2 DAC0 and DAC1 is buffered at full voltage range (DACxCTL = $87). RVA3 The module is enabled and ADC is running at 6.
PAGE 1206
Electrical Characteristics Table A-16. Run and Wait Current Characteristics (Junction Temperature From +150°C To +160°C) Conditions are: VDDR=5.5V, TA=150°C, see Table A-13. and Table A-14. Num C Rating Symbol Min Typ Max Unit S12GN16, S12GN32 1 C IDD Run Current (code execution from RAM) IDDRr 12.7 mA 2 C IDD Run Current (code execution from flash) IDDRf 13.2 mA 3 C IDD Wait Current IDDW 7.4 mA MC9S12G Family Reference Manual, Rev.1.
PAGE 1207
Electrical Characteristics Table A-17. Full Stop Current Characteristics Conditions are: Typ: VDDX,VDDR,VDDA=5V, Max: VDDX,VDDR,VDDA=5.5V API see Table A-13. Num C Rating Symbol Min Typ Max Unit S12GN16, S12GN32 Stop Current API disabled 1 P -40°C IDDS 14.4 24 µA 2 P 25°C IDDS 16.5 28 µA 3 P 150°C IDDS 120 320 µA 4 C 160°C IDDS 140 µA 5 C -40°C IDDS 18.5 µA 6 C 25°C IDDS 21.
PAGE 1208
Electrical Characteristics Table A-18. Pseudo Stop Current Characteristics Conditions are: VDDX=5V, VDDR=5V, VDDA=5V, RTI and COP and API enabled, see Table A-12.
PAGE 1209
Electrical Characteristics This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-19. ADC Operating Characteristics Supply voltage 3.13 V < VDDA < 5.5 V, -40oC < TJ < TJmax1 Num C 1 2 D Reference potential Low High Symbol Min Typ Max Unit VRL VRH VSSA VDDA/2 — — VDDA/2 VDDA V V 2 D Voltage difference VDDX to VDDA ∆VDDX –2.35 0 0.
PAGE 1210
Electrical Characteristics in an error (10-bit resolution) of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance of up to 10Kohm are allowed. A.4.2.4 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance.
PAGE 1211
Electrical Characteristics A.4.3.1 ADC Accuracy Definitions For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL ( i ) = -------------------------- – 1 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ V –V n 0 DNL ( i ) = --------------------- – n 1LSB i=1 MC9S12G Family Reference Manual, Rev.1.
PAGE 1212
Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $FF $3FC $3FB $3FA $3F9 $FE $3F8 $3F7 $3F6 $3F5 10-Bit Resolution $3F3 9 Ideal Transfer Curve 2 8 8-Bit Resolution $FD $3F4 7 10-Bit Transfer Curve 6 5 1 4 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 45 55 60 65 70 75 80 85 90 95 100 105 110 115 120 5000 + Vin mV Figure A-1.
PAGE 1213
Electrical Characteristics Table A-21. ADC Conversion Performance 5V range (Junction Temperature From –40°C To +150°C) S12GNA16, S12GNA32, S12GAS48, S12GA64, S12GA96, S12GA128, S12GA192 and S12GA240 Supply voltage 4.5V < VDDA < 5.5 V, -40oC < TJ < 150oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions.
PAGE 1214
Electrical Characteristics Table A-22. ADC Conversion Performance 5V range (Junction Temperature From +150°C To +160°C) S12GNA16, S12GNA32 Supply voltage 4.5V < VDDA < 5.5 V, +150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C 1 Min Typ Max Unit 1 C Resolution 12-Bit LSB 1.
PAGE 1215
Electrical Characteristics Table A-23. ADC Conversion Performance 5V range (Junction Temperature From –40°C To +150°C) S12GN16, S12GN32, S12GN48, S12G48, S12G64, S12G96, S12G128, S12G192, and S12G240 Supply voltage 4.5V < VDDA < 5.5 V, -40oC < TJ < 150oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions.
PAGE 1216
Electrical Characteristics Table A-24. ADC Conversion Performance 5V range (Junction Temperature From +150°C To +160°C) S12GN16, S12GN32 Supply voltage 4.5V < VDDA < 5.5 V, 150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions. Rating1 Num C Symbol Min Typ Max Unit 1 C Resolution 10-Bit LSB 5 mV 2 C Differential Nonlinearity 10-Bit DNL ±0.
PAGE 1217
Electrical Characteristics 2 These values include the quantization error which is inherently 1/2 count for any A/D converter. Table A-26. ADC Conversion Performance 3.3V range (Junction Temperature From +150°C To +160°C) S12GNA16, S12GNA32 Supply voltage 3.13V < VDDA < 4.5 V, 150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.0MHz The values are tested to be valid with no port AD output drivers switching simultaneous with conversions.
PAGE 1218
Electrical Characteristics 1 The 8-bit mode operation is structurally tested in production test. Absolute values are tested in 10-bit mode. These values include the quantization error which is inherently 1/2 count for any A/D converter. 3 LQFP 48 and bigger 4 LQFP 32 and smaller 2 Table A-28. ADC Conversion Performance 3.3V range (Junction Temperature From +150°C To +160°C) S12GN16, S12GN32 Supply voltage 3.13V < VDDA < 4.5 V, 150oC < TJ < 160oC, VREF = VRH - VRL = VDDA, fADCCLK = 8.
PAGE 1219
Electrical Characteristics Table A-29. ADC Conversion Performance 5V range, RVA enabled Supply voltage VDDA =5.0 V, -40oC < TJ < 150oC. VRH = 5.0V. fADCCLK = 0.25 .. 2MHz 1 The values are tested to be valid with no port AD/C output drivers switching simultaneous with conversions. Num C Rating Symbol Min Typ Max Unit 1 P Resolution 12-Bit LSB 0.61 2 P Differential Nonlinearity 12-Bit DNL ±3 ±4 counts 3 P Integral Nonlinearity 12-Bit INL ±3.
PAGE 1220
Electrical Characteristics A.4.3.2 ADC Analog Input Parasitics Figure A-2. ADC Analog Input Parasitics VDDA sampling time is 4 to 24 adc clock cycles of 0.25MHz to 8MHz -> 96µs >= tsample >= 500ns Ileakp < 0.5µA PAD00PAD11 Ileakn < 0.5µA Ctop 920Ω < Rpath < 9.9KΩ (incl parasitics) 3.7pF < S/H Cap < 6.
PAGE 1221
Electrical Characteristics Table A-31. ACMP Electrical Characteristics (Junction Temperature From –40°C To +150°C) Characteristics noted under conditions 3.13V <= VDDA <= 5.5V, -40oC < Tj < 150oC unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25˚C under nominal conditions unless otherwise noted. Num C 1 D C Ratings Supply Current of ACMP module disabled module enabled ∆Vin > 0.
PAGE 1222
Electrical Characteristics Figure A-3. Input Offset and Hysteresis V Hysteresis Offset ACMPM ACMPP ACMPO t A.6 DAC Characteristics This section describes the electrical characteristics of the digital to analog converter. Table A-33. Static Electrical Characteristics - DAC_8B5V Characteristics noted under conditions 3.13V <= VDDA <= 5.5V>, -40˚C < Tj < 150˚C >, VRH=VDDA, VRL=VSSA unless otherwise noted.
PAGE 1223
Electrical Characteristics Table A-33. Static Electrical Characteristics - DAC_8B5V Characteristics noted under conditions 3.13V <= VDDA <= 5.5V>, -40˚C < Tj < 150˚C >, VRH=VDDA, VRL=VSSA unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25˚C under nominal conditions unless otherwise noted.
PAGE 1224
Electrical Characteristics A.7.1.1 Erase Verify All Blocks (Blank Check) (FCMD=0x01) The time required to perform a blank check on all blocks is dependent on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command.
PAGE 1225
Electrical Characteristics FTMRG64K1, FTMRG48K1: 1 t pcheck = 16700 ⋅ --------------------f NVMBUS FTMRG32K1, FTMRG16K1: 1 t pcheck = 33400 ⋅ --------------------f NVMBUS Assuming that no non-blank location is found, then the time to erase verify a EEPROM block is given by: FTMRG240K2, FTMRG192K2: 1 t dcheck = 2620 ⋅ --------------------f NVMBUS FTMRG128K1, FTMRG96K1: 1 t dcheck = 2620 ⋅ --------------------f NVMBUS FTMRG64K1, FTMRG48K1: 1 t dcheck = 1540 ⋅ --------------------f NVMBUS FTMRG32K1, FTMR
PAGE 1226
Electrical Characteristics A.7.1.5 Program P-Flash (FCMD=0x06) The programming time for a single phrase of four P-Flash words and the two seven-bit ECC fields is dependent on the bus frequency, fNVMBUS, as well as on the NVM operating frequency, fNVMOP.
PAGE 1227
Electrical Characteristics A.7.1.
PAGE 1228
Electrical Characteristics FTMRG128K1, FTMRG96K1: 1 1 t uns ≈ 100070 ⋅ ------------------ + 33500 ⋅ --------------------f NVMBUS f NVMOP FTMRG64K1, FTMRG48K1: 1 1 t uns ≈ 100070 ⋅ ------------------ + 18300 ⋅ --------------------f NVMBUS f NVMOP FTMRG32K1, FTMRG16K1: 1 1 t uns ≈ 100070 ⋅ ------------------ + 9600 ⋅ --------------------f NVMBUS f NVMOP A.7.1.11 Verify Backdoor Access Key (FCMD=0x0C) The maximum verify backdoor access key time is given by: 1 t = 520 ⋅ --------------------f NVMBUS A.7.
PAGE 1229
Electrical Characteristics A.7.1.15 Program EEPROM (FCMD=0x11) EEPROM programming time is dependent on the number of words being programmed and their location with respect to a row boundary since programming across a row boundary requires extra steps.
PAGE 1230
Electrical Characteristics Table A-34. NVM Timing Characteristics Num C Rating Symbol Min Typ1 Max2 Unit3 1 Bus frequency fNVMBUS 1 — 25 MHz 2 Operating frequency fNVMOP 0.8 1.0 1.
PAGE 1231
Electrical Characteristics Num C Rating Symbol Min Typ1 Max2 Unit3 8 D P-Flash sector erase time tpera — 20 26 ms 9 D P-Flash phrase programming time tppgm — 185 200 µs 4 tdera — 5 26 ms D EEPROM erase verify (blank check) time (FTMRG240K2, TMRG192K2) tdcheck — — 2620 tcyc EEPROM erase verify (blank check) time (FTMRG128K1, FTMRG96K1) tdcheck — — 2620 tcyc EEPROM erase verify (blank check) time (FTMRG64K1, FTMRG48K1) tdcheck — — 1540 tcyc EEPROM erase verify (bl
PAGE 1232
Electrical Characteristics Table A-35.
PAGE 1233
Electrical Characteristics 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-4. Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).
PAGE 1234
Electrical Characteristics A.8.2 Electrical Characteristics for the PLL Table A-36. PLL Characteristics Conditions are shown in Table A-15 unless otherwise noted Num C Rating Symbol Min fVCORST Typ Max Unit 8 25 MHz 50 MHz 1 D VCO frequency during system reset 2 C VCO locking range fVCO 32 3 C Reference Clock fREF 1 4 D Lock Detection |∆Lock| 0 1.5 %1 5 D Un-Lock Detection |∆unl| 0.5 2.
PAGE 1235
Electrical Characteristics Table A-39. IRC1M Characteristics (Junction Temperature From +150°C To +160°C, all packages) Conditions are: Temperature option W (see Table A-4) Num C 1 Rating C Internal Reference Frequency, factory trimmed Symbol Min Typ Max Unit fIRC1M_TRIM 0.987 1 1.013 MHz MC9S12G Family Reference Manual, Rev.1.
PAGE 1236
Electrical Characteristics A.10 Electrical Characteristics for the Oscillator (XOSCLCP) Table A-40. XOSCLCP Characteristics (Junction Temperature From –40°C To +150°C) Conditions are shown in Table A-4 unless otherwise noted Num C Min Typ Max Unit 16 MHz C Nominal crystal or resonator frequency fOSC 4.0 2 P Startup Current iOSC 100 3a C Oscillator start-up time (4MHz)1 tUPOSC — 2 10 ms 3b C Oscillator start-up time (8MHz)1 tUPOSC — 1.
PAGE 1237
Electrical Characteristics Table A-41. XOSCLCP Characteristics (Junction Temperature From +150°C To +160°C) Conditions are shown in Table A-4 unless otherwise noted Num C Min Typ Max Unit 16 MHz C Nominal crystal or resonator frequency fOSC 4.0 2 C Startup Current iOSC 100 3a C Oscillator start-up time (4MHz)1 tUPOSC — 2 10 ms 3b C Oscillator start-up time (8MHz)1 tUPOSC — 1.
PAGE 1238
Electrical Characteristics A.12 Electrical Specification for Voltage Regulator Table A-43. Voltage Regulator Characteristics (Junction Temperature From –40°C To +150°C) Num C Symbol Min Typical Max Unit 1 P Input Voltages VVDDR,A 3.13 — 5.5 V P VDDA Low Voltage Interrupt Assert Level 1 VDDA Low Voltage Interrupt Deassert Level VLVIA VLVID 4.04 4.19 4.23 4.38 4.40 4.49 V V 3 P VDDX Low Voltage Reset Deassert 2 3 4 VLVRXD — 3.05 3.
PAGE 1239
Electrical Characteristics Table A-44. Voltage Regulator Characteristics (Junction Temperature From +150°C To +160°C) Num C Symbol Min Typical Max Unit 1 C Input Voltages VVDDR,A 3.13 — 5.5 V C VDDA Low Voltage Interrupt Assert Level 1 VDDA Low Voltage Interrupt Deassert Level VLVIA VLVID 4.04 4.19 4.23 4.38 4.40 4.49 V V 3 C VDDX Low Voltage Reset Deassert 2 3 4 VLVRXD — 3.05 3.13 V 4 C VDDX Low Voltage Reset Assert 2 3 4 VLVRXA 2.95 3.
PAGE 1240
Electrical Characteristics A.13 Chip Power-up and Voltage Drops LVI (low voltage interrupt), POR (power-on reset) and LVRs (low voltage reset) handle chip power-up or drops of the supply voltage. Figure A-6. Chip Power-up and Voltage Drops V VDDA/VDDX VLVID VLVIA VDD VLVRD VLVRA VPORD t LVI LVI enabled LVI disabled due to LVR POR LVR A.14 MSCAN Table A-45.
PAGE 1241
Electrical Characteristics A.15 SPI Timing This section provides electrical parametrics and ratings for the SPI. In Table A-46 the measurement conditions are listed. Table A-46. Measurement Conditions Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to TJmax Description Drive mode Load capacitance CLOAD1, on all outputs Thresholds for delay measurement points 1 Value Unit Full drive mode — 50 pF (35% / 65%) VDDX V Timing specified for equal load on all SPI output pins.
PAGE 1242
Electrical Characteristics In Figure A-8 the timing diagram for master mode with transmission format CPHA=1 is depicted. SS (Output) 1 2 12 13 12 13 3 SCK (CPOL = 0) (Output) 4 4 SCK (CPOL = 1) (Output) 5 MISO (Input) 6 MSB IN2 Port Data LSB IN 11 9 MOSI (Output) Bit MSB-1. . . 1 Master MSB OUT2 Bit MSB-1. . . 1 Master LSB OUT Port Data 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB. Figure A-8.
PAGE 1243
Electrical Characteristics In Table A-47 the timing characteristics for master mode are listed. Table A-47. SPI Master Mode Timing Characteristics Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to TJmax.
PAGE 1244
Electrical Characteristics In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. SS (Input) 3 1 2 12 13 12 13 SCK (CPOL = 0) (Input) 4 4 SCK (CPOL = 1) (Input) See Note 7 MOSI (Input) Slave 5 8 11 9 MISO (Output) MSB OUT Bit MSB-1 . . . 1 Slave LSB OUT 6 MSB IN Bit MSB-1 . . . 1 LSB IN NOTE: Not defined Figure A-10. SPI Slave Timing (CPHA = 1) MC9S12G Family Reference Manual, Rev.1.
PAGE 1245
Electrical Characteristics In Table A-48 the timing characteristics for slave mode are listed. Table A-48. SPI Slave Mode Timing Characteristics Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to TJmax.
PAGE 1246
Electrical Characteristics Table A-49. Measurement Conditions Description Symbol Value NVM activity Unit none MC9S12G Family Reference Manual, Rev.1.
PAGE 1247
Detailed Register Address Map Appendix B Detailed Register Address Map Revision History Version Number Revision Date Rev 0.05 30-Aug-2010 Rev 0.06 18-Oct-2010 • Updated ADC registers in Appendix B, “Detailed Register Address Map”. Rev 0.07 9-Nov-2010 • Updated CPMU registers in Appendix B, “Detailed Register Address Map”. Rev 0.08 4-Dec-2010 • Updated PIM registers in Appendix B, “Detailed Register Address Map”. Rev 0.09 24-Apr-2012 • Typos and formatting B.
PAGE 1248
Detailed Register Address Map 0x000A–0x000B Memory Map Control (MMC) Map 1 of 2 Address Name 0x000A Reserved 0x000B MODE R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDPEE PUPDE PUPCE PUPBE PUPAE MODC 0x000C–0x000D Port Integration Module (PIM) Map 2 of 6 Address Name 0x000C PUCR 0x000D Reserved Bit 7 R W R W 0 0 Bit 6 BKPUE Bit 5 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
PAGE 1249
Detailed Register Address Map 0x001A–0x001B Device ID Register (PARTIDH/PARTIDL) Address Name 0x001A PARTIDH 0x001B PARTIDL Bit 7 Bit 6 Bit 5 Bit 4 R W R W Bit 3 Bit 2 Bit 1 Bit 0 PARTIDH PARTIDL 0x001C–0x001F Port Integration Module (PIM) Map 3 of 6 Address Name 0x001C ECLKCTL 0x001D Reserved 0x001E IRQCR 0x001F Reserved R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 IRQE I
PAGE 1250
Detailed Register Address Map 0x0020–0x002F Debug Module (DBG) Address Name 0x0029 DBGXAH 0x002A DBGXAM 0x002B DBGXAL 0x002C DBGADH 0x002D DBGADL 0x002E DBGADHM 0x002F DBGADLM R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0 0 0 0 0 0 Bit 1 Bit 0 Bit 17 Bit 16 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2
PAGE 1251
Detailed Register Address Map 0x0034–0x003F Clock and Power Management (CPMU) Map 1 of 2 Address Name 0x003D Reserved 0x003E Reserved 0x003F CPMU ARMCOP R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 FOC6 0 FOC5 0 FOC4 0 FOC3 0 FOC2 0 FOC1 0 FOC0 OC7M6 OC7M5
PAGE 1252
Detailed Register Address Map 0x0040–0x067 Timer Module (TIM) R Bit 15 W TCxH – TCxL R Bit 7 W R 0 0x0060 PACTL W R 0 0x0061 PAFLG W R 0x0062 PACNTH PACNT15 W R 0x0063 PACNTL PACNT7 W R 0x0064Reserved 0x006B W R 0x006C OCPD OCPD7 W R 0x006D Reserved W R 0x006E PTPSR PTPS7 W R 0x006F Reserved W 0x0050 – 0x005F Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 PAOVF PAIF PACNT14 PACNT13 PACNT1
PAGE 1253
Detailed Register Address Map 0x0070–0x09F Analog to Digital Converter (ADC) Address Name R 0x007A ATDSTAT2H W R 0x007B ATDSTAT2L W R 0x007C ATDDIENH W R 0x007D ATDDIENL W R 0x007E ATDCMPHTH W R 0x007F ATDCMPHTL W R 0x0080ATDDR0 0x0091 W R 0x0082ATDDR1 0x0083 W R 0x0084ATDDR2 0x0085 W R 0x0086ATDDR3 0x0087 W R 0x0088ATDDR4 0x0089 W R 0x008AATDDR5 0x008B W R 0x008CATDDR6 0x008D W R 0x008EATDDR7 0x008F W R 0x0090ATDDR8 0x0091 W R 0x0092ATDDR9 0x0093 W R 0x0094ATDDR10 0x0095 W R 0x0096ATDDR11 0x0097 W R 0x0
PAGE 1254
Detailed Register Address Map 0x00A0–0x0C7 Pulse-Width-Modulator (PWM) Address 0x00A0 0x00A1 0x00A2 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 0x00AA 0x00AB 0x00AC 0x00AD 0x00AE 0x00AF 0x0B0 0x00B1 0x00B2 0x00B3 0x00B4 0x00B5 0x00B6 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R PWME PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W R PWMPOL PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W R PWMCLK PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 W R 0 0 PWMPRCLK PCKB2 PCKB1 PCKB0
PAGE 1255
Detailed Register Address Map 0x00A0–0x0C7 Pulse-Width-Modulator (PWM) 0x00B7 PWMPER3 0x00B8 PWMPER4 0x00B9 PWMPER5 0x00BA PWMPER6 0x00BB PWMPER7 0x00BC PWMDTY0 0x00BD PWMDTY1 0x00BE PWMDTY2 0x00BF PWMDTY3 0x00C0 PWMDTY4 0x00C1 PWMDTY5 0x00C2 PWMDTY6 0x00C3 PWMDTY7 0x00C40x00C7 Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6
PAGE 1256
Detailed Register Address Map 0x00C8–0x0CF Serial Communication Interface (SCI0) 0x00CC SCI0SR1 0x00CD SCI0SR2 0x00CE SCI0DRH 0x00CF SCI0DRL R W R W R W R W TDRE AMAP R8 TC RDRF 0 0 T8 R7 T7 R6 T6 IDLE OR NF FE PF TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 RAF 0x00D0–0x0D7 Serial Communication Interface (SCI1) Address Name 0x00D0 SCI1BDH 0x00D0 SCI1ASR1 0x00D1 SCI1BDL 0x00D1 SCI1ACR1 0x00D2 SCI1CR1 0x00D2 SCI1ACR2 0x00D3 SC
PAGE 1257
Detailed Register Address Map 0x00D8–0x0DF Serial Peripheral Interface (SPI0) 0x00DC SPI0DRH 0x00DD SPI0DRL 0x00DE0x00DF Reserved R W R W R W R15 T15 R7 T7 R14 T14 R6 T6 R13 T13 R5 T5 R12 T12 R4 T4 R11 T11 R3 T3 R10 T10 R2 T2 R9 T9 R1 T1 R8 T8 R0 T0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0x00E0–0x0E7 Reserved Address Name 0x00E00x00E7 Reserved R W 0x00E8–0x0EF Serial Communication Interface (SCI2) Address Name 0x00E8 SCI2BDH 0x00E8 SCI2ASR1
PAGE 1258
Detailed Register Address Map 0x00F0–0x0F7 Serial Peripheral Interface (SPI1) 0x00F2 SPI1BR 0x00F3 SPI1SR 0x00F4 SPI1DRH 0x00F5 SPI1DRL 0x00F60x00F7 Reserved R W R W R W R W R W 0 SPPR2 SPPR1 SPPR0 SPIF 0 SPTEF MODF R15 T15 R7 T7 R14 T14 R6 T6 R13 T13 R5 T5 0 SPR2 SPR1 SPR0 0 0 0 0 R12 T12 R4 T4 R11 T11 R3 T3 R10 T10 R2 T2 R9 T9 R1 T1 R8 T8 R0 T0 0x00F8–0x0FF Serial Peripheral Interface (SPI2) Address Name 0x00F8 SPI2CR1 0x00F9 SPI2CR2 0x00FA SPI2BR 0x00FB SPI2SR
PAGE 1259
Detailed Register Address Map 0x0100–0x0113 Flash Module (FTMRG) Address Name 0x0107 FERSTAT 0x0108 FPROT 0x0109 DFPROT 0x010A FCCOBHI 0x010B FCCOBLO 0x010C Reserved 0x010D Reserved 0x010E Reserved 0x010F Reserved 0x0110 FOPT 0x0111 Reserved 0x0112 Reserved 0x0113 Reserved Bit 7 Bit 1 Bit 0 DFDIF SFDIF FPLDIS FPLS1 FPLS0 DPS3 DPS2 DPS1 DPS0 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PAGE 1260
Detailed Register Address Map 0x0140–0x017F CAN Controller (MSCAN) Address Name Bit 7 Bit 6 R 0x0140 CANCTL0 RXFRM W R 0x0141 CANCTL1 CANE W R 0x0142 CANBTR0 SJW1 W R 0x0143 CANBTR1 SAMP W R 0x0144 CANRFLG WUPIF W R 0x0145 CANRIER WUPIE W R 0 0x0146 CANTFLG W R 0 0x0147 CANTIER W R 0 0x0148 CANTARQ W R 0 0x0149 CANTAAK W R 0 0x014A CANTBSEL W R 0 0x014B CANIDAC W R 0 0x014C Reserved W R 0 0x014D CANMISC W R RXERR7 0x014E CANRXERR W R TXERR7 0x014F CANTXERR W R 0x0150CANIDAR0–3 AC7 0x0153 W R 0x0154CANI
PAGE 1261
Detailed Register Address Map 0x0180–0x023F Reserved Address 0x01800x023F Name Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0x0240–0x025F Port Integration Module (PIM) Map 4 of 6 Address Name 0x0240 PTT 0x0241 PTIT 0x0242 DDRT 0x0243 Reserved 0x0244 PERT 0x0245 PPST 0x02460x0247 Reserved 0x0248 PTS 0x0249 PTIS 0x024A DDRS 0x024B Reserved 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F PRR0 0x0250 PTM 0x0251 PTIM 0x0252 DDRM
PAGE 1262
Detailed Register Address Map 0x0240–0x025F Port Integration Module (PIM) Map 4 of 6 Address Name 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 PKGCR 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B Reserved 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP Bit 7 R 0 W R 0 W R 0 W R APICLKS7 W R PTP7 W R PTIP7 W R DDRP7 W R 0 W R PERP7 W R PPSP7 W R PIEP7 W R PIFP7 W Bit 6 Bit 5 Bit 4 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 PERM3 PERM2 PERM1 PERM0 0 0 0 PPSM3 PPSM2 PPSM1 PPSM0 0
PAGE 1263
Detailed Register Address Map 0x0262–0x0275 Port Integration Module (PIM) Map 5 of 6 Address Name 0x026A DDRJ 0x026B Reserved 0x026C PERJ 0x026D PPSJ 0x026E PIEJ 0x026F PIFJ 0x0270 PT0AD 0x0271 PT1AD 0x0272 PTI0AD 0x0273 PTI1AD 0x0274 DDR0AD 0x0275 DDR1AD R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 0 0 0 0 0 0 0 0 PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PE
PAGE 1264
Detailed Register Address Map 0x0277–0x027F Port Integration Module (PIM) Map 6 of 6 Address Name 0x027C PIE0AD 0x027D PIE1AD 0x027E PIF0AD 0x027F PIF1AD R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1
PAGE 1265
Detailed Register Address Map 0x02F0–0x02FF Clock and Power Management (CPMU) Map 2 of 2 0x02FB CPMUPROT 0x02FC Reserved 0x02FD0x02FF Reserved R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 2 Bit 1 Bit 0 PROT 0x0300–0x03BF Reserved Address Name 0x03000x03BF Reserved R W 0x03C0–0x03C7 Digital to Analog Converter (DAC0) Address Name 0x03C0 DAC0CTL 0x03C1 0x03C2 0x03C3 0x03
PAGE 1266
Detailed Register Address Map 0x03C8–0x03CF Digital to Analog Converter (DAC1) 0x03CC Reserved 0x03CD Reserved 0x03CE Reserved 0x03CF Reserved R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0x03D0–0x03FF Reserved Address 0x03D00x03FF Name Reserved R W MC9S12G Family Reference Manual, Rev.1.
PAGE 1267
Ordering and Shipping Information Appendix C Ordering and Shipping Information Revision History Version Number Revision Date Description of Changes Rev 0.01 2-Jan-2009 Rev 0.02 22-Nov-2012 Added temperature option W Rev 0.03 25-Jan-2013 • Updated C.1, “Ordering Information” (added KGD option) • Added C.2, “KGD Shipping Information” Rev 0.04 1-Feb-2013 • Removed C.2, “KGD Shipping Information” C.
PAGE 1268
Ordering and Shipping Information S W 9 S12 G128 F0 M LL R Tape & Reel: R = Tape & Reel No R = No Tape & Reel Package Option: TJ = 20 TSSOP LC = 32 LQFP LF = 48 LQFP FT = 48 QFN LH = 64 LQFP LL = 100 LQFP Temperature Option: C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C W = -40˚C to 150˚C Mask set identifier Suffix: First digit usually references wafer fab Second digit usually differentiates mask rev (This suffix is omitted in generic part numbers) Device Title Controller Family Main Memory
PAGE 1269
Package and Die Information Appendix D Package and Die Information Revision History Version Number Revision Date Description of Changes Rev 0.01 2-Jan-2009 Initial release Rev 0.02 25-Jan-2013 • Added D.7, “KGD Information” Rev 0.03 31-Jan-2013 • Updated , “Bondpad Coordinates” MC9S12G Family Reference Manual, Rev.1.
PAGE 1270
Package and Die Information D.1 100 LQFP Mechanical Dimensions MC9S12G Family Reference Manual, Rev.1.
PAGE 1271
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1272
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1273
Package and Die Information D.2 64 LQFP Mechanical Dimensions MC9S12G Family Reference Manual, Rev.1.
PAGE 1274
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1275
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1276
Package and Die Information D.3 48 LQFP Mechanical Dimensions MC9S12G Family Reference Manual, Rev.1.
PAGE 1277
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1278
Package and Die Information D.4 48 QFN Mechanical Dimensions MC9S12G Family Reference Manual, Rev.1.
PAGE 1279
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1280
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1281
Package and Die Information D.5 32 LQFP Mechanical Dimensions MC9S12G Family Reference Manual, Rev.1.
PAGE 1282
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1283
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1284
Package and Die Information D.6 20 TSSOP Mechanical Dimensions MC9S12G Family Reference Manual, Rev.1.
PAGE 1285
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1286
Package and Die Information MC9S12G Family Reference Manual, Rev.1.
PAGE 1287
Package and Die Information D.7 KGD Information Bondpad Coordinates Table D-1. Bondpad Coordinates Die Pad Bond Post Die Pad X Coordinate Die Pad Y Coordinate Function 1 1 -1832.06 1347.5 PJ[6] 2 2 -1832.06 1223.5 PJ[5] 3 3 -1832.06 1116.5 PJ[4] 4 4 -1832.06 1009.5 PA[0] 5 5 -1832.06 902.5 PA[1] 6 6 -1832.06 795.5 PA[2] 7 7 -1832.06 688.5 PA[3] 8 8 -1832.06 603.5 RESET 9 9 -1832.06 496.5 VDDX1 10 10 -1832.06 369 VDDR 11 11 -1832.06 241.
PAGE 1288
Package and Die Information Table D-1. Bondpad Coordinates Die Pad Bond Post Die Pad X Coordinate Die Pad Y Coordinate Function 28 28 -1315.5 -1472.06 PB[3] 29 29 -1134.5 -1472.06 PP[0] 30 30 -964.5 -1472.06 PP[1] 31 31 -794.5 -1472.06 PP[2] 32 32 -660.5 -1472.06 PP[3] 33 33 -526.5 -1472.06 PP[4] 34 34 -404.5 -1472.06 PP[5] 35 35 -292.5 -1472.06 PP[6] 36 36 -190.5 -1472.06 PP[7] 37 37 -105.5 -1472.06 VDDX3 38 38 -0.5 -1472.06 VSSX3 39 39 93.
PAGE 1289
Package and Die Information Table D-1. Bondpad Coordinates Die Pad Bond Post Die Pad X Coordinate Die Pad Y Coordinate Function 58 58 -1832.06 -467.5 PAD[9] 59 59 -1832.06 -360.5 PAD[2] 60 60 -1832.06 -253.5 PAD[10] 61 61 -1832.06 -148.5 PAD[3] 62 62 -1832.06 -41.5 PAD[11] 63 63 -1832.06 65.5 PAD[4] 64 64 -1832.06 172.5 PAD[12] 65 65 -1832.06 279.5 PAD[5] 66 66 -1832.06 386.5 PAD[13] 67 67 -1832.06 493.5 PAD[6] 68 68 -1832.06 598.
PAGE 1290
Package and Die Information Table D-1. Bondpad Coordinates Die Pad Bond Post Die Pad X Coordinate Die Pad Y Coordinate Function 88 87 128.5 -1472.06 PS[5] 89 88 14.5 -1472.06 PS[6] 90 89 -99.5 -1472.06 PS[7] 91 90 -213.5 -1472.06 VSSX2 92 91 -318.5 -1472.06 VDDX2 93 92 -428.5 -1472.06 PM[0] 94 93 -548.5 -1472.06 PM[1] 95 94 -688.5 -1472.06 PD[4] 96 95 -828.5 -1472.06 PD[5] 97 96 -998.5 -1472.06 PD[6] 98 97 -1168.5 -1472.06 PD[7] 99 98 -1338.
PAGE 1291
PAGE 1292
How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.