Datasheet

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 159
• Control register for free-running clock outputs
•
A standard port pin has the following minimum features:
• Input/output selection
• 3.15 V - 5 V digital and analog input
• Input with selectable pullup or pulldown device
Optional features supported on dedicated pins:
• Open drain for wired-or connections
• Key-wakeup feature: External pin interrupt with glitch filtering, which can also be used for wakeup
from stop mode.
2.1.4 Block Diagram
Figure 2-1. Block Diagram
2.2 PIM Routing - External Signal Description
This section lists and describes the signals that do connect off-chip.
Table 2-3 shows the availability of I/O port pins for each group in the largest offered package option.
Table 2-3. Port Pin Availability (in largest package) per Device
Port
Device Group
G1
(100 pin)
G2
(64 pin)
G3
(48 pin)
A 7-0 - -
B 7-0 - -
Peripheral
Module
PIM
Ports
PIM
Routing
0
1
n
Pin #0
Package Code
Pin Routing (20 TSSOP only)
Pin #n
Pin Enable, Data
Pin Enable, Data
Data
Data
Control
Control