Datasheet

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 163
E PE1 XTAL
- CPMU OSC signal
TXD0
I/O SCI transmit
IOC3
I/O Timer channel
PWM1
O PWM channel
ETRIG1
I ADC external trigger
[PE1]
I/O GPIO
PE0 EXTAL
- CPMU OSC signal
RXD0
I SCI receive
IOC2
I/O Timer channel
PWM0
O PWM channel
ETRIG0
I ADC external trigger
[PE0]
I/O GPIO
T PT7-PT6 IOC7-IOC6
I/O Timer channel
[PTT7:PTT6]
I/O GPIO
PT5-PT4 IOC5-IOC4
I/O Timer channel
[PTT5:PTT4]
I/O GPIO
PT3-PT2 IOC3-IOC2
I/O Timer channel
[PTT3:PTT2]
I/O GPIO
PT1
IRQ I Maskable level- or
falling-edge sensitive
interrupt
IOC1
I/O Timer channel
[PTT1]
I/O GPIO
PT0
XIRQ I Non-maskable
level-sensitive interrupt
IOC0
I/O Timer channel
[PTT0]
I/O GPIO
Table 2-4. Signals and Priorities
Port Pin Signal
Signals per Device and Package
(signal priority on pin from top to bottom)
Legend
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
G64 / GA64 / G48 / GA48
GN48
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
G64 / GA64 / G48 / GA48
GN48
GN32 / GNA32
GN16 / GNA16
G64 / G48
GN48
GN32
GN16
GN32
GN16
Signal available on pin
Routing option on pin
Routing reset location
Not available on pin
100 64 48 32 20 I/O Description