Datasheet

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual, Rev.1.23
164 Freescale Semiconductor
S PS7
SS0 I/O SPI slave select
TXD0
I/O SCI transmit
PWM5
O PWM channel
PWM3
O PWM channel
ECLK
O Free-running clock
API_EXTCLK
O API Clock
ETRIG3
I ADC external trigger
[PTS7]
I/O GPIO
PS6 SCK0
I/O SPI serial clock
IOC5
I/O Timer channel
IOC3
I/O Timer channel
[PTS6]
I/O GPIO
PS5 MOSI0
I/O SPI master out/slave in
IOC4
I/O Timer channel
IOC2
I/O Timer channel
[PTS5]
I/O GPIO
PS4 MISO0
I/O SPI master in/slave out
RXD0
I SCI receive pin
PWM4
O PWM channel
PWM2
O PWM channel
ETRIG2
I ADC external trigger
[PTS4]
I/O GPIO
PS3 TXD1
I/O SCI transmit
[PTS3]
I/O GPIO
PS2 RXD1
I SCI receive
[PTS2]
I/O GPIO
PS1 TXD0
I/O SCI transmit
[PTS1]
I/O GPIO
PS0 RXD0
I SCI receive
[PTS0]
I/O GPIO
Table 2-4. Signals and Priorities
Port Pin Signal
Signals per Device and Package
(signal priority on pin from top to bottom)
Legend
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
G64 / GA64 / G48 / GA48
GN48
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
G64 / GA64 / G48 / GA48
GN48
GN32 / GNA32
GN16 / GNA16
G64 / G48
GN48
GN32
GN16
GN32
GN16
Signal available on pin
Routing option on pin
Routing reset location
Not available on pin
100 64 48 32 20 I/O Description