Datasheet

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 169
AD PAD7 ACMPM
I ACMP inverting input (-)
AN7
I ADC analog
[PT1AD7]/
KWAD7
I/O GPIO with interrupt
PAD6 ACMPP
I ACMP non-inv. input (+)
AN6
I ADC analog
[PT1AD6]/
KWAD6
I/O GPIO with interrupt
PAD5 ACMPO
O ACMP unsync. dig. out
ACMPM
I ACMP inverting input (-)
AN5
I ADC analog
TXD0
I/O SCI transmit
IOC3
I/O Timer channel
PWM3
O PWM channel
ETRIG3
I ADC external trigger
[PT1AD5]/
KWAD5
I/O GPIO with interrupt
PAD4 ACMPP
I ACMP non-inv. input (+)
AN4
I ADC analog
RXD0
I SCI receive
IOC2
I/O Timer channel
PWM2
O PWM channel
ETRIG2
I ADC external trigger
[PT1AD4]/
KWAD4
I/O GPIO with interrupt
PAD3 ACMPO
O ACMP unsync. dig. out
AN3
I ADC analog
[PT1AD3]/
KWAD3
I/O GPIO with interrupt
PAD2-PAD0 AN2-AN0
I ADC analog
[PT1AD2:
PT1AD0]/
KWAD2-
KWAD0
I/O GPIO with interrupt
Table 2-4. Signals and Priorities
Port Pin Signal
Signals per Device and Package
(signal priority on pin from top to bottom)
Legend
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
G64 / GA64 / G48 / GA48
GN48
GA240 / GA192
G240 / G192
G128 / GA128 / G96 / GA96
G64 / GA64 / G48 / GA48
GN48
GN32 / GNA32
GN16 / GNA16
G64 / G48
GN48
GN32
GN16
GN32
GN16
Signal available on pin
Routing option on pin
Routing reset location
Not available on pin
100 64 48 32 20 I/O Description