Datasheet

Interrupt Module (S12SINTV1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 283
Figure 6-1. INT Block Diagram
6.2 External Signal Description
The INT module has no external signals.
6.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
6.3.1 Register Descriptions
This section describes in address order all the INT registers and their individual bits.
6.3.1.1 Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
Address: 0x0120
76543210
R
IVB_ADDR[7:0]
W
Reset 11111111
Figure 6-2. Interrupt Vector Base Register (IVBR)
Wake Up
IVBR
Interrupt
Requests
Interrupt Requests
CPU
Vector
Address
Peripheral
To CPU
Priority
Decoder
Non I bit Maskable Channels
I bit Maskable Channels