Datasheet

S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
320 Freescale Semiconductor
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
8.3.2.4 Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 8-7. DBGTCR Field Descriptions
Field Description
6
TSOURCE
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU
system is secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested
3–2
TRCMOD
Trace Mode Bits — See Section 8.4.5.2, “Trace Modes for detailed Trace Mode descriptions. In Normal Mode,
change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries
into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored.
In Compressed Pure PC mode the program counter value for each instruction executed is stored. See Table 8-8.
0
TALIGN
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
Table 8-8. TRCMOD Trace Mode Bit Encoding
TRCMOD Description
00 Normal
01 Loop1
10 Detail
11 Compressed Pure PC
Address: 0x0023
76543210
R000000
ABCM
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-6. Debug Control Register2 (DBGC2)
Table 8-9. DBGC2 Field Descriptions
Field Description
1–0
ABCM[1:0]
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in Table 8-10.