Datasheet

S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
324 Freescale Semiconductor
The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2). Thus with
SC[3:0]=1101 a simultaneous match0/match1 transitions to final state.
8.3.2.7.2 Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control
Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
DBGXCTL control register.
1010 Reserved
1011 Reserved
1100 Reserved
1101 Either Match0 or Match2 to Final State........Match1 to State2
1110 Reserved
1111 Reserved
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
Table 8-17. DBGSCR2 Field Descriptions
Field Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State2, based upon the match event.
Table 8-18. State2 —Sequencer Next State Selection
SC[3:0] Description (Unspecified matches have no effect)
0000 Match0 to State1....... Match2 to State3.
0001 Match1 to State3
0010 Match2 to State3
0011 Match1 to State3....... Match0 Final State
0100 Match1 to State1....... Match2 to State3.
Table 8-16. State1 Sequencer Next State Selection
SC[3:0] Description (Unspecified matches have no effect)