Datasheet

S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 325
The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2).
8.3.2.7.3 Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control
Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
DBGXCTL control register.
0101 Match2 to Final State
0110 Match2 to State1..... Match0 to Final State
0111 Either Match0 or Match1 to Final State
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Either Match0 or Match1 to Final State........Match2 to State3
1101 Reserved
1110 Reserved
1111 Either Match0 or Match1 to Final State........Match2 to State1
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-11. Debug State Control Register 3 (DBGSCR3)
Table 8-19. DBGSCR3 Field Descriptions
Field Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State3, based upon the match event.
Table 8-20. State3 — Sequencer Next State Selection
SC[3:0] Description (Unspecified matches have no effect)
0000 Match0 to State1
Table 8-18. State2 —Sequencer Next State Selection
SC[3:0] Description (Unspecified matches have no effect)