Datasheet

S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 327
register bytes (three address bus compare registers and a control register). Comparator C consists of four
register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register.
Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be
written. The control register for comparator B differs from those of comparators A and C.
8.3.2.8.1 Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Table 8-21. Comparator Register Layout
0x0028 CONTROL Read/Write Comparators A,B and C
0x0029 ADDRESS HIGH Read/Write Comparators A,B and C
0x002A ADDRESS MEDIUM Read/Write Comparators A,B and C
0x002B ADDRESS LOW Read/Write Comparators A,B and C
0x002C DATA HIGH COMPARATOR Read/Write Comparator A only
0x002D DATA LOW COMPARATOR Read/Write Comparator A only
0x002E DATA HIGH MASK Read/Write Comparator A only
0x002F DATA LOW MASK Read/Write Comparator A only
Address: 0x0028
76543210
R
SZE SZ TAG BRK RW RWE NDB COMPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-13. Debug Comparator Control Register DBGACTL (Comparator A)
Address: 0x0028
76543210
R
SZE SZ TAG BRK RW RWE
0
COMPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B)
Address: 0x0028
76543210
R0 0
TAG BRK RW RWE
0
COMPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C)