Datasheet

S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
330 Freescale Semiconductor
8.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See Table 8-24 for visible register encoding.
Write: If DBG not armed. See Table 8-24 for visible register encoding.
8.3.2.8.4 Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See Table 8-24 for visible register encoding.
Write: If DBG not armed. See Table 8-24 for visible register encoding.
Address: 0x002A
76543210
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 8-17. Debug Comparator Address Mid Register (DBGXAM)
Table 8-26. DBGXAM Field Descriptions
Field Description
7–0
Bit[15:8]
Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the
selected comparator compares the address bus bits [15:8] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Address: 0x002B
76543210
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 8-18. Debug Comparator Address Low Register (DBGXAL)
Table 8-27. DBGXAL Field Descriptions
Field Description
7–0
Bits[7:0]
Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the
selected comparator compares the address bus bits [7:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one