Datasheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 371
10.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU.
10.3.1 Module Memory Map
The S12CPMU registers are shown in Figure 10-3.
Addres
s
Name Bit 7 6 5 4 3 2 1 Bit 0
0x0034
CPMU
SYNR
R
VCOFRQ[1:0] SYNDIV[5:0]
W
0x0035
CPMU
REFDIV
R
REFFRQ[1:0]
00
REFDIV[3:0]
W
0x0036
CPMU
POSTDIV
R0 0 0
POSTDIV[4:0]
W
0x0037 CPMUFLG
R
RTIF PORF LVRF LOCKIF
LOCK
ILAF OSCIF
UPOSC
W
0x0038 CPMUINT
R
RTIE
00
LOCKIE
00
OSCIE
0
W
0x0039 CPMUCLKS
R
PLLSEL PSTP
0
COP
OSCSEL1
PRE PCE
RTI
OSCSEL
COP
OSCSEL0
W
0x003A CPMUPLL
R0 0
FM1 FM0
00 0 0
W
0x003B CPMURTI
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x003C CPMUCOP
R
WCOP RSBCK
000
CR2 CR1 CR0
W WRTMASK
0x003D
RESERVEDCP
MUTEST0
R0 0 0 000 0 0
W
0x003E
RESERVEDCP
MUTEST1
R0 0 0 000 0 0
W
0x003F
CPMU
ARMCOP
R0 0 0 000 0 0
W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02F0 RESERVED
R0 0 0 000 0 0
W
0x02F1
CPMU
LVCTL
R 0 0 0 0 0 LVDS
LVIE LVIF
W
0x02F2
CPMU
APICTL
R
APICLK
00
APIES APIEA APIFE APIE APIF
W
= Unimplemented or Reserved
Figure 10-3. CPMU Register Summary