Datasheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 375
10.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: Anytime if PLLSEL=1. Else write has no effect.
10.3.2.4 S12CPMU Flags Register (CPMUFLG)
This register provides S12CPMU status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
0x0036
76543210
R000
POSTDIV[4:0]
W
Reset 00000011
= Unimplemented or Reserved
Figure 10-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
0x0037
76543210
R
RTIF PORF LVRF LOCKIF
LOCK
ILAF OSCIF
UPOSC
W
Reset 0 Note 1 Note 2 0 0 Note 3 0 0
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
= Unimplemented or Reserved
Figure 10-7. S12CPMU Flags Register (CPMUFLG)
f
PLL
f
VCO
POSTDIV 1+()
-----------------------------------------
=
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
f
PLL
f
VCO
4
---------------
=
f
bus
f
PLL
2
-------------
=
If PLL is selected (PLLSEL=1)