Datasheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual, Rev.1.23
378 Freescale Semiconductor
10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)
This register controls S12CPMU clock selection.
Read: Anytime
Write:
1. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode).
2. All bits in Special Mode (if PROT=0).
3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0).
4. COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place.
If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1
or insufficient OSCCLK quality), then COPOSCSEL0 can be set once again.
5. COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once is taken.
COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with
COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for
other clock domains: for instance core clock etc.).
NOTE
After writing CPMUCLKS register, it is strongly recommended to read
back CPMUCLKS register to make sure that write of PLLSEL,
RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful.
0x0039
76543210
R
PLLSEL PSTP
0
COP
OSCSEL1
PRE PCE
RTI
OSCSEL
COP
OSCSEL0
W
Reset 10000000
= Unimplemented or Reserved
Figure 10-9. S12CPMU Clock Select Register (CPMUCLKS)