Datasheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 391
10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.
Read: Anytime
Write: Anytime
0x02F2
76543210
R
APICLK
00
APIES APIEA APIFE APIE APIF
W
Reset 00000000
= Unimplemented or Reserved
Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
Table 10-16. CPMUAPICTL Field Descriptions
Field Description
7
APICLK
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous Clock (ACLK) used as source.
1 Bus Clock used as source.
4
APIES
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin
API_EXTCLK as shown in Figure 10-18. See device level specification for connectivity of API_EXTCLK pin.
0 If APIEA and APIFE are set, at the external pin API_EXTCLK periodic high pulses are visible at the end of
every selected period with the size of half of the minimum period (APIR=0x0000 in Table 10-20).
1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API
Period.
3
APIEA
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
2
APIFE
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
1
APIE
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
0
APIF
Autonomous Periodical Interrupt Flag — After each time-out of the API (time-out rate is configured in the
CPMUAPIRH/L registers) the interrupt flag APIF is set to 1. This flag can only be cleared by writing a 1. Writing
a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.
0 API time-out has not yet occurred.
1 API time-out has occurred.