Datasheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual, Rev.1.23
412 Freescale Semiconductor
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
.
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the
RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
Figure 10-34. RESET Timing
10.5.2.1 Clock Monitor Reset
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency f
CMFA
(see device electrical characteristics for values), the S12CPMU
Table 10-27. Reset Vector Selection
Sampled RESET Pin
(256 cycles after
release)
Oscillator monitor
fail pending
COP
time out
pending
Vector Fetch
1 0 0 POR
LVR
Illegal Address Reset
External pin
RESET
1 1 X Clock Monitor Reset
1 0 1 COP Reset
0 X X POR
LVR
Illegal Address Reset
External pin
RESET
)
(
)
PLLCLK
512 cycles
256 cycles
S12_CPMU drives
possibly
RESET
driven low
externally
)
(
(
RESET
S12_CPMU releases
f
VCORST
RESET pin low
RESET pin
f
VCORST