Datasheet
Analog-to-Digital Converter (ADC12B12CV2)
MC9S12G Family Reference Manual, Rev.1.23
498 Freescale Semiconductor
14.1.3 Block Diagram
Figure 14-1. ADC12B12C Block Diagram
VSSA
AN6
Analog
MUX
Mode and
Successive
Approximation
Register (SAR)
Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
and DAC
Sample & Hold
VDDA
VRL
VRH
Sequence Complete
+
-
Comparator
Clock
Prescaler
Bus Clock
ATD Clock
AN5
AN4
AN3
AN1
AN0
AN7
ETRIG0
(See device speciļ¬-
cation for availability
ETRIG1
ETRIG2
ETRIG3
and connectivity)
Timing Control
ATDDIENATDCTL1
Trigger
Mux
Interrupt
Compare Interrupt
AN2
AN8
AN9
AN10
AN11
ATD 8
ATD 9
ATD 10
ATD 11