Datasheet

Analog-to-Digital Converter (ADC10B16CV2)
MC9S12G Family Reference Manual, Rev.1.23
524 Freescale Semiconductor
15.1.3 Block Diagram
Figure 15-1. ADC10B16C Block Diagram
VSSA
AN9
Analog
MUX
Mode and
Successive
Approximation
Register (SAR)
Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
and DAC
Sample & Hold
VDDA
VRL
VRH
Sequence Complete
+
-
Comparator
Clock
Prescaler
Bus Clock
ATD Clock
AN7
AN6
AN5
AN10
ETRIG0
(See device specifi-
cation for availability
ETRIG1
ETRIG2
ETRIG3
and connectivity)
Timing Control
ATDDIENATDCTL1
Trigger
Mux
Interrupt
Compare Interrupt
AN4
AN11
AN12
AN13
AN14
ATD 8
ATD 9
ATD 10
ATD 11
ATD 13
ATD 14
ATD 12
ATD 15
AN3
AN2
AN1
AN0
AN8
AN15