Datasheet

MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 573
Chapter 17
Digital Analog Converter (DAC_8B5V)
17.1 Revision History
Glossary
Table 17-1. Revision History Table
Rev. No.
(Item No.)
Data Sections
Affected
Substantial Change(s)
0.1 28-Oct.-09 all Initial Version
0.4 28-Oct.-09 (Thomas Becker) all Initial Version
0.5 12-Nov.-09 (Thomas Becker) all Reworked all sections, renamed pin names
0.6 17-Nov.-09 (Thomas Becker) 1.2.4 Added CPU stop mode
0.7 18-Nov.-09 (Thomas Becker) 1.2, 1.3 Update block diagram, removed analog and digital submodule,
added section 1.3
0.8 04-Dec.-09 (Thomas Becker) 1.4.2 - changed reset value of FVR bit to 1’b1
- added new bit “Load” to DACCTL register
- removed S3 switch description
0.9 05-Jan.-10 (Thomas Becker) 1.3, 1.4.2.1, 1.5 - renamed register bit “Load” to “Drive”, request by analog team
- renamed pin DAC to DACU
0.91 13-Jan.-10 (Thomas Becker) 1.4.2.3 - added debug register
0.92 12-Feb.-10 (Thomas Becker) all - fixed typo
1.0 12-Apr.-10 1.4.2.1 Added DACCTL register bit DACDIEN
1.01 04-May-10, Table 1.2,
Section 1.4
Replaced VRL,VRL with variable
correct wrong figure, table numbering
1.02 12-May-10 Section 1.4 replaced ipt_test_mode with ips_test_access
new description/address of DACDEBUG register
1.1 25-May-10 17.4.2.1 Removed DACCTL register bit DACDIEN
1.2 25-Jun.-10 17.4 Correct table and figure title format
1.3 29-Jul.-10 17.2 Fixed typos
1.4 17-Nov.-10 17.2.2 Update the behavior of the DACU pin during stop mode
Table 17-2. Terminology
Term Meaning
DAC Digital to Analog Converter
VRL Low Reference Voltage