Datasheet

Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12G Family Reference Manual, Rev.1.23
608 Freescale Semiconductor
Module Base + 0x0014 to Module Base + 0x0017 Access: User read/write
1
1
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
Figure 18-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
Table 18-24. CANIDMR0–CANIDMR3 Register Field Descriptions
Field Description
7-0
AM[7:0]
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
Module Base + 0x001C to Module Base + 0x001F Access: User read/write
1
1
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
76543210
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 00000000
Figure 18-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Table 18-25. CANIDMR4–CANIDMR7 Register Field Descriptions
Field Description
7-0
AM[7:0]
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit