Datasheet

Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 611
Read:
• For transmit buffers, anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• For receive buffers, only when RXF flag is set (see Section 18.3.2.5, “MSCAN Receiver Flag
Register (CANRFLG)”).
Write:
• For transmit buffers, anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation
18.3.3.1 Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE,
and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
= Unused, always read ‘x’
Figure 18-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Name
Bit 7 654321Bit 0
IDR0
0x00X0
R
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
W
IDR1
0x00X1
R
ID2 ID1 ID0 RTR IDE (=0)
W
IDR2
0x00X2
R
W
IDR3
0x00X3
R
W
= Unused, always read ‘x’
Figure 18-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Register
Name
Bit 7 654321Bit0