Datasheet

Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 615
18.3.3.2 Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
18.3.3.3 Data Length Register (DLR)
This register keeps the data length field of the CAN frame.
Module Base + 0x00X2
76543210
R
W
Reset: xxxxxxxx
= Unused; always read ‘x’
Figure 18-32. Identifier Register 2 — Standard Mapping
Module Base + 0x00X3
76543210
R
W
Reset: xxxxxxxx
= Unused; always read ‘x’
Figure 18-33. Identifier Register 3 — Standard Mapping
Module Base + 0x00X4 to Module Base + 0x00XB
76543210
R
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
W
Reset: xxxxxxxx
Figure 18-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
Table 18-33. DSR0–DSR7 Register Field Descriptions
Field Description
7-0
DB[7:0]
Data bits 7-0