Datasheet

Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12G Family Reference Manual, Rev.1.23
646 Freescale Semiconductor
s
19.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 19.4.2.5, “Left Aligned Outputs” and Section 19.4.2.6, “Center Aligned Outputs” for a more
detailed description of the PWM output modes.
Read: Anytime
Write: Anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Table 19-7. PWMPRCLK Field Descriptions
Field Description
6–4
PCKB[2:0]
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for all channels. These
three bits determine the rate of clock B, as shown in Table 19-8.
2–0
PCKA[2:0]
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for all channels. These
three bits determine the rate of clock A, as shown in Table 19-8.
Table 19-8. Clock A or Clock B Prescaler Selects
PCKA/B2 PCKA/B1 PCKA/B0 Value of Clock A/B
0 0 0 Bus clock
0 0 1 Bus clock / 2
0 1 0 Bus clock / 4
0 1 1 Bus clock / 8
1 0 0 Bus clock / 16
1 0 1 Bus clock / 32
1 1 0 Bus clock / 64
1 1 1 Bus clock / 128
Module Base + 0x0004
76543210
R
CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
W
Reset 0 0 0 00000
Figure 19-7. PWM Center Align Enable Register (PWMCAE)