Datasheet

Serial Communication Interface (S12SCIV5)
MC9S12G Family Reference Manual, Rev.1.23
676 Freescale Semiconductor
20.3.2.6 SCI Control Register 2 (SCICR2)
Read: Anytime
Write: Anytime
1 1 Reserved
Module Base + 0x0003
76543210
R
TIE TCIE RIE ILIE TE RE RWU SBK
W
Reset 0 0 0 00000
Figure 20-9. SCI Control Register 2 (SCICR2)
Table 20-10. SCICR2 Field Descriptions
Field Description
7
TIE
Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate
interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
6
TCIE
Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate
interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
5
RIE
Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag,
OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
4
ILIE
Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
3
TE
Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by
the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
2
RE
Receiver Enable Bit — RE enables the SCI receiver.
0 Receiver disabled
1 Receiver enabled
Table 20-9. Bit Error Mode Coding
BERRM1 BERRM0 Function