Datasheet

Timer Module (TIM16B8CV3)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor 773
Figure 23-30. Detailed Timer Block Diagram
PRESCALER
CHANNEL 0
IOC0 PIN
16-BIT COUNTER
LOGIC
PR[2:1:0]
DIVIDE-BY-64
TC0
EDGE
DETECT
PACNT(hi):PACNT(lo)
PAOVF
PEDGE
PAOVI
TEN
PAEN
16-BIT COMPARATOR
TCNT(hi):TCNT(lo)
CHANNEL 1
TC1
16-BIT COMPARATOR
16-BIT COUNTER
INTERRUPT
LOGIC
TOF
TOI
C0F
C1F
EDGE
DETECT
IOC1 PIN
LOGIC
EDGE
DETECT
CxF
CHANNEL7
TC7
16-BIT COMPARATOR C7F
IOC7 PIN
LOGIC
EDGE
DETECT
OM:OL0
TOV0
OM:OL1
TOV1
OM:OL7
TOV7
EDG1A EDG1B
EDG7A
EDG7B
EDG0B
TCRE
PAIF
CLEAR COUNTER
PAIF
PAI
INTERRUPT
LOGIC
CxI
INTERRUPT
REQUEST
PAOVF
CH. 7 COMPARE
CH.7 CAPTURE
CH. 1 CAPTURE
MUX
CLK[1:0]
PACLK
PACLK/256
PACLK/65536
IOC1 PIN
IOC0 PIN
IOC7 PIN
PACLK
PACLK/256
PACLK/65536
TE
CH. 1 COMPARE
CH. 0COMPARE
CH. 0 CAPTURE
PA INPUT
CHANNEL2
EDG0A
channel 7 output
compare
IOC0
IOC1
IOC7
Bus Clock
PAOVF
PAOVI
TOF
C0F
C1F
C7F
MUX
PRE-PRESCALER
PTPSR[7:0]
Bus Clock
1
0
PRNT
Maximum possible channels, scalable from 0 to 7.
Pulse Accumulator is available only if channel 7 exists.
MUX
PAMOD
PEDGE