SC16C2552B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 03 — 12 February 2009 Product data sheet 1. General description The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data, and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC16C2552B is pin compatible with the PC16552 and ST16C2552.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 3. Ordering information Table 1. Ordering information Type number SC16C2552BIA44 Package Name Description Version PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 4.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 5. Pinning information 40 CTSA 41 DSRA 42 CDA 1 43 RIA D0 TXRDYA 2 44 VCC D2 D1 3 D3 5 4 D4 6 5.1 Pinning D5 7 39 RXA D6 8 38 TXA D7 9 37 DTRA A0 10 36 RTSA XTAL1 11 35 MFA SC16C2552BIA44 GND 12 34 INTA XTAL2 13 33 VCC A1 14 32 TXRDYB A2 15 31 RIB CHSEL 16 30 CDB INTB 17 Fig 2.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 2. Pin description …continued Symbol Pin Type Description D0 2 I/O D1 3 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D2 4 I/O D3 5 I/O D4 6 I/O D5 7 I/O D6 8 I/O D7 9 I/O DSRA 41 I DSRB 29 I DTRA 37 O DTRB 27 O GND 12, 22 I Signal and power ground.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 2. Pin description …continued Symbol Pin Type Description RTSA 36 O RTSB 23 O Request to Send A, B (active LOW). These outputs are associated with individual UART channels A through B. A logic 0 on the RTSn pin indicates the transmitter is ready to transmit data.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 6. Functional description The SC16C2552B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 6.2 Internal registers The SC16C2552B provides two sets of internal registers (A and B) consisting of 13 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C2552B FIFO may hold more characters than the programmed trigger level.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 5. Baud rate generator programming table using a 1.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs made available at the user data interface D0 to D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7. Register descriptions Table 6 details the assigned bit functions for the SC16C2552B internal registers. The assigned bit functions are further defined in Section 7.1 through Section 7.11. Table 6.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0) to the TSR and UART via the THR, providing that the THR is empty.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive FIFO has reached the programmed trigger level.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit 3 = 0) Set and enable the interrupt for each single transmit or receive operation and is similar to the 16C450 mode.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 8. Bit FIFO Control Register bits description …continued Symbol 3 (continued) Description Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.4 Interrupt Status Register (ISR) The SC16C2552B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits and the parity are selected by writing the appropriate bits in this register. Table 12. Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 16. Modem Control Register bits description Bit Symbol Description 7:5 MCR[7:5] reserved; initialized to a logic 0 4 MCR[4] Loopback. Enable the local Loopback mode (diagnostics).
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2552B and the CPU. Table 17. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem or other peripheral device to which the SC16C2552B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.9 Scratchpad Register (SPR) The SC16C2552B provides a temporary data register to store 8 bits of user information. 7.10 Alternate Function Register (AFR) This is a read/write register used to select specific modes of MF operation and to allow both UART register’s sets to be written concurrently. Table 19. Alternate Function Register bit description Bit Symbol Description 7:3 AFR[7:3] Not used.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.11 SC16C2552B external reset condition Table 21. Reset state for registers Register Reset state IER IER[7:0] = 0 ISR ISR[7:1] = 0; ISR[0] = 1 LCR LCR[7:0] = 0 MCR MCR[7:0] = 0 LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR MSR[7:4] = input signals; MSR[3:0] = 0 FCR FCR[7:0] = 0 AFR AFR[7:0] = 0 Table 22.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 9. Static characteristics Table 24. Static characteristics Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %; unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V VCC = 3.3 V VCC = 5.0 V Min Max Min Max Min Max Unit VIL(clk) clock LOW-level input voltage −0.3 +0.45 −0.3 +0.6 −0.5 +0.6 V VIH(clk) clock HIGH-level input voltage 1.8 VCC 2.4 VCC 3.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 10. Dynamic characteristics Table 25. Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %; unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V VCC = 3.3 V VCC = 5.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 25. Dynamic characteristics …continued Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %; unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V t28d delay from start to reset TXRDY [3] tRESET RESET pulse width [4] N baud rate divisor VCC = 3.3 V VCC = 5.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs t6h valid address A0 to A2 CHSEL t7h t6s active CS t7d t7w IOR t9d active t12h t12d D0 to D7 data 002aaa127 Fig 6.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs tWL tWH external clock tw(clk) 002aac357 1 f XTAL1 = --------------t w ( clk ) Fig 8. External clock timing start bit RXA, RXB parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits t20d active INTA, INTB t21d active IOR 16 baud rate clock 002aae287 Fig 9. Receive timing SC16C2552B_3 Product data sheet © NXP B.V.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit D0 RXA, RXB parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 t25d active data ready RXRDYA, RXRDYB t26d active IOR 002aae288 Fig 10.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit parity bit data bits (0 to 7) TXA, TXB D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits active transmitter ready INTA, INTB t22d t24d t23d IOW active active 16 baud rate clock 002aae290 Fig 12.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits (0 to 7) D0 TXA, TXB parity bit D1 D2 D3 D4 D5 D6 stop bit D7 5 data bits 6 data bits 7 data bits IOW active t28d D0 to D7 byte #16 t27d TXRDYA, TXRDYB FIFO full 002aae292 Fig 14. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C2552B_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 β 18 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 12.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 28.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 14. Revision history Table 29. Revision history Document ID Release date Data sheet status Change notice Supersedes SC16C2552B_3 20090212 Product data sheet - SC16C2552B-02 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Table 29. Revision history …continued Document ID Modifications: (continued) Release date • Data sheet status Change notice Supersedes Section 10.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
SC16C2552B NXP Semiconductors 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . .