Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSC16C550BIB48,151

1. General description

The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for

serial data communications. Its principal function is to convert parallel data into serial data,

and vice versa. The UART can handle serial data rates up to 3 Mbit/s.

The SC16C550B is pin compatible with the ST16C550, TL16C550 and PC16C550, and it

will power-up to be functionally equivalent to the 16C450. The SC16C550B also provides

DMA mode data transfers through FIFO trigger levels and the TXRDY

and RXRDY

signals (TXRDY

and RXRDY are not supported in the HVQFN32 package). On-board

status registers provide the user with error indications, operational status, and modem

interface control. System interrupts may be tailored to meet user requirements. An internal

loopback capability allows on-board diagnostics.

The SC16C550B operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range,

and is available in plastic HVQFN32, DIP40, PLCC44 and LQFP48 packages.

2. Features and benefits

 5 V, 3.3 V and 2.5 V operation

 Industrial temperature range

 After reset, all registers are identical to the typical 16C450 register set

 Capable of running with all existing generic 16C450 software

 Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,

PC16C450/550

 Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at 2.5 V

 5 V tolerant on input only pins

 16 byte transmit FIFO

 16 byte receive FIFO with error flags

 Programmable auto-RTS

and auto-CTS

 In auto-CTS mode, CTS controls transmitter

 In auto-RTS

mode, RX FIFO contents and threshold control RTS

 Automatic hardware flow control

 Software selectable baud rate generator

 Four selectable Receive FIFO interrupt trigger levels

 Standard modem interface

 Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

 Independent receiver clock input

 Transmit, Receive, Line Status, and Data Set interrupts independently controlled

SC16C550B

5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs

Rev. 6 — 16 December 2014 Product data sheet

1. For data bus pins D7 to D0, see Table 24 “Limiting values”.

Summary of content (49 pages)

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SC16C550B 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Rev. 6 — 16 December 2014 Product data sheet 1. General description The SC16C550B is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 4.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 5. Pinning information 40 CTS 41 DSR 42 DCD 43 RI n.c. 1 44 VDD D1 D0 D2 4 2 D3 5 3 D4 6 5.1 Pinning D5 7 39 RESET D6 8 38 OUT1 D7 9 37 DTR RCLK 10 36 RTS RX 11 35 OUT2 SC16C550BIA44 n.c. 12 34 n.c. TX 13 33 INT AS 28 TXRDY 27 IOR 25 DDIS 26 n.c.
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SC16C550B NXP Semiconductors 37 n.c. 38 CTS 39 DSR 40 DCD 41 RI 42 VDD 43 D0 44 D1 45 D2 46 D3 47 D4 48 n.c. 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs n.c. 1 36 n.c. D5 2 35 RESET D6 3 34 OUT1 D7 4 33 DTR RCLK 5 32 RTS n.c. 6 RX 7 TX 8 29 RXRDY CS0 9 28 A0 CS1 10 27 A1 CS2 11 26 A2 31 OUT2 SC16C550BIB48 30 INT BAUDOUT 12 AS 24 TXRDY 23 DDIS 22 n.c. 21 IOR 20 IOR 19 VSS 18 IOW 17 IOW 16 XTAL2 15 n.c. 13 Fig 4. XTAL1 14 25 n.c.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 5.2 Pin description Table 2. Symbol Pin description Pin Type Description I Register select. A2 to A0 are used during read and write operations to select the UART register to read from or write to. Refer to Table 3 for register addresses and refer to AS description. PLCC44 LQFP48 DIP40 HVQFN32 A0 31 28 28 19 A1 30 27 27 18 A2 29 26 26 17 AS 28 24 25 - I Address strobe.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description PLCC44 LQFP48 DIP40 HVQFN32 DSR[2] 41 39 37 25 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the Modem Status Register. Bit 1 (DSR) of the Modem Status Register indicates DSR has changed levels since the last read from the Modem Status Register.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description PLCC44 LQFP48 DIP40 HVQFN32 RI[2] 43 41 39 27 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the Modem Status Register. Bit 2 (RI) of the Modem Status Register indicates that RI has changed from a LOW to a HIGH level since the last read from the Modem Status Register.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description I Write inputs. When either IOW or IOW is active (LOW or HIGH, respectively) and while the UART is selected, the CPU is allowed to write control words or data into a selected UART register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied to its inactive level (that is, IOW tied LOW or IOW tied HIGH).
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.1 Internal registers The SC16C550B provides 12 internal registers for monitoring and control. These registers are shown in Table 3.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.3 Autoflow control Autoflow control is comprised of auto-CTS and auto-RTS (see Figure 6). With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.3.3 Enabling autoflow control and auto-CTS Autoflow control is enabled by setting MCR[5] and MCR[1]. Table 5. Enabling autoflow control and auto-CTS MCR[5] MCR[1] Selection 1 1 auto RTS and CTS 1 0 auto CTS 0 X disable 6.3.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs RX byte 14 byte 15 Start byte 16 Stop Start byte 18 Stop RTS released after the first data bit of byte 16 RTS IOR 002aaa051 (1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth byte.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.5 Programmable baud rate generator The SC16C550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. The SC16C550B can support a standard data rate of 921.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 6. Baud rates using 1.8432 MHz or 3.072 MHz crystal Using 1.8432 MHz crystal Desired baud Divisor for rate 16 clock Using 3.072 MHz crystal Baud rate error Desired baud Divisor for rate 16 clock Baud rate error 50 2304 50 3840 75 1536 75 2560 110 1047 0.026 110 1745 0.026 134.5 857 0.058 134.5 1428 0.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 6.7 Loopback mode The internal loopback capability allows on-board diagnostics. In the loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally. MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the loopback mode, OUT1 (bit 2) and OUT2 (bit 3) in the MCR register control the modem RI and DCD inputs, respectively.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7. Register descriptions Table 9 details the assigned bit functions for the twelve SC16C550B internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.10. Table 9.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Holding Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the THR, providing that the THR or TSR is empty.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.3.2 FIFO mode Table 11. FIFO Control Register bits description Bit Symbol Description 7:6 FCR[7] (MSB), RX trigger. These bits are used to set the trigger level for the receive FCR[6] (LSB) FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 12.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 12. RX trigger levels FCR[7] FCR[6] RX FIFO trigger level (bytes) 0 0 1 0 1 4 1 0 8 1 1 14 7.4 Interrupt Status Register (ISR) The SC16C550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15. Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhance Feature mode enable.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Table 16. LCR[5] LCR[4] LCR[3] Parity selection X X 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity ‘1’ 1 1 1 forced parity ‘0’ Table 17. Product data sheet LCR[2] stop bit length LCR[2] Word length Stop bit length (bit times) 0 5, 6, 7, 8 1 1 5 11⁄2 1 6, 7, 8 2 Table 18.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Modem Control Register bits description Bit Symbol Description 7 MCR[7] reserved; set to ‘0’ 6 MCR[6] reserved; set to ‘0’ 5 MCR[5] Auto flow control enable. 4 MCR[4] Loopback. Enable the local loopback mode (diagnostics).
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C550B and the CPU. Table 20. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C550B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. Table 21.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 7.9 Scratchpad Register (SPR) The SC16C550B provides a temporary data register to store 8 bits of user information. 7.10 SC16C550B external reset conditions Table 22. Reset state for registers Register Reset state IER IER[7:0] = 0 ISR ISR[7:1] = 0; ISR[0] = 1 LCR LCR[7:0] = 0 MCR MCR[7:0] = 0 LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR MSR[7:4] = input signals; MSR[3:0] = 0 FCR FCR[7:0] = 0 Table 23.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 9. Static characteristics Table 25. Static characteristics Tamb = 40 C to +85 C; tolerance of VDD =  10 %, unless otherwise specified. Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Min Max Min Max Min Max Unit VIL(clk) clock LOW-level input voltage 0.3 +0.45 0.3 +0.6 0.5 +0.6 V VIH(clk) clock HIGH-level input voltage 1.8 VDD 2.4 VDD 3.0 VDD V VIL LOW-level input voltage 0.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 10.1 Timing diagrams t4w AS t5s t5h valid address A0 to A2 t6s t6h CS2 CS1, CS0 valid t7d t7h t7w t8d t9d active IOR, IOR t11d t11h active DDIS t12h t12d D0 to D7 data 002aaa331 Fig 12. General read timing when using AS signal t4w AS t5s t5h valid address A0 to A2 t6s CS2 CS1, CS0 valid t13d t14d IOW, IOW t6h t13h t13w t15d active t16s D0 to D7 t16h data 002aaa332 Fig 13.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs valid address A0 to A2 valid address t6s' t6s' t7h' active CS t7h' t7w active t7w t9d active IOR t12h t12d t12d t12h data D0 to D7 002aaa333 Fig 14. General read timing when AS is tied to VSS valid address A0 to A2 valid address t6s' CS t7h' active active t13w IOW t15d t13w active t16s D0 to D7 t7h' t6s' t16h t16s t16h data 002aaa334 Fig 15.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs IOW active t17d RTS DTR change of state change of state DCD CTS DSR change of state change of state t18d t18d INT active active active t19d active IOR active active t18d change of state RI 002aaa347 Fig 16. Modem input/output timing tw2 tw1 EXTERNAL CLOCK tw3 002aaa112 1 f XTAL = -----t w3 Fig 17.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits t20d 7 data bits active INT t21d active IOR 16 baud rate clock 002aaa113 Fig 18. Receive timing start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 t25d active data ready RXRDY t26d active IOR 002aab063 Fig 19.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs start bit D0 RX parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit D7 first byte that reaches the trigger level t25d active data ready RXRDY t26d active IOR 002aab064 Fig 20.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs start bit TX D0 IOW active D0 to D7 byte #1 parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 t28d t27d active transmitter ready TXRDY transmitter not ready 002aaa580 Fig 22.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 11. Package outline seating plane DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 21 40 pin 1 index E 1 20 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.7 0.51 4 1.70 1.14 0.53 0.38 0.36 0.23 52.5 51.5 inches 0.19 0.02 0.16 0.067 0.045 0.021 0.015 0.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 β 18 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e b 9 y y1 C v M C A B w M C 16 L 17 8 e e2 Eh 1/2 1 terminal 1 index area e 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 12.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Soldering of through-hole mount packages 13.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 13.4 Package related soldering information Table 29. Suitability of through-hole mount IC packages for dipping and wave soldering Package Soldering method Dipping Wave CPGA, HCPGA - suitable DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1] PMFP[2] - not suitable [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 15. Revision history Table 31. Revision history Document ID Release date Data sheet status Change notice Supersedes SC16C550B_6 20141216 Product data sheet - SC16C550B_5 Modifications: • Table 9 “SC16C550B internal registers”: changed MCR bit 3 from “OUT2” to “OUT2, INT enable”; updated Table note 4.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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SC16C550B NXP Semiconductors 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 6.7 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . .