Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSC16C554BIB64,151

1. General description

The SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and

Transmitter (QUART) used for serial data communications. Its principal function is to

convert parallel data into serial data and vice versa. The UART can handle serial data

rates up to 5 Mbit/s. It comes with an Intel (16 mode) or Motorola (68 mode) interface.

The SC16C554B/554DB is pin compatible with the ST16C554 and TL16C554 and it will

power-up to be functionally equivalent to the 16C454. Programming of control registers

enables the added features of the SC16C554B/554DB. Some of these added features are

the 16-byte receive and transmit FIFOs, four receive trigger levels. The

SC16C554B/554DB also provides DMA mode data transfers through FIFO trigger levels

and the TXRDY

and RXRDY signals. (TXRDY and RXRDY signals are not available in the

HVQFN48 package.) On-board status registers provide the user with error indications,

operational status, and modem interface control. System interrupts may be tailored to

meet user requirements. An internal loopback capability allows on-board diagnostics.

The SC16C554B/554DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature

range, and is available in plastic PLCC68, LQFP64, LQFP80, and HVQFN48 packages.

On the HVQFN48 package only, channel C has all the modem pins. Channels A and B

have only RTSn

and CTSn pins and channel D does not have any modem pin.

2. Features and benefits

 4 channel UART

 5 V, 3.3 V and 2.5 V operation

 Industrial temperature range (−40 °C to +85 °C)

 The SC16C554B is pin and software compatible with the industry-standard

ST16C454/554, ST68C454/554, ST16C554, TL16C554

 The SC16C554DB is pin and software compatible with ST16C554D, and software

compatible with ST16C454/554, ST16C554, TL16C554

 Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

 5 V tolerant on input only pins

 16-byte transmit FIFO

 16-byte receive FIFO with error flags

 Programmable auto-RTS

and auto-CTS

 In auto-CTS mode, CTS controls transmitter

 In auto-RTS

mode, RX FIFO contents and threshold control RTS

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte

FIFOs

Rev. 4 — 8 June 2010 Product data sheet

1. For data bus pins D7 to D0, see Table 24 “Limiting values”.

Summary of content (58 pages)

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SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 4 — 8 June 2010 Product data sheet 1. General description The SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and Transmitter (QUART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. It comes with an Intel (16 mode) or Motorola (68 mode) interface.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 4.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 5. Pinning information 5.1 Pinning 61 CDD 62 RID 63 RXD 64 VCC 65 INTSEL 66 D0 67 D1 D3 1 68 D2 D4 2 D7 5 D6 GND 6 D5 RXA 7 3 RIA 8 4 CDA 9 5.1.
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SC16C554B/554DB NXP Semiconductors 61 CDD 62 RID 63 RXD 64 VCC 65 n.c. 66 D0 67 D1 D3 1 68 D2 D4 2 D7 5 D6 GND 6 D5 RXA 7 3 RIA 8 4 CDA 9 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs DSRA 10 60 DSRD CTSA 11 59 CTSD DTRA 12 58 DTRD VCC 13 57 GND RTSA 14 56 RTSD IRQ 15 55 n.c. CS 16 54 n.c. TXA 17 53 TXD SC16C554DBIA68 68 mode R/W 18 TXB 19 52 n.c. 51 TXC A3 20 50 A4 n.c. 21 49 n.c. RTSB 22 48 RTSC GND 23 47 VCC Fig 4.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 49 CDD 50 RID 51 RXD 52 VCC 53 D0 54 D1 55 D2 56 D3 57 D4 58 D5 59 D6 60 D7 61 GND 62 RXA 63 RIA 64 CDA 5.1.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 61 n.c. 62 DSRC 63 CTSC 64 DTRC 65 VCC 66 RTSC 67 INTC 68 CSC 69 TXC 70 IOR 71 n.c. 1 60 n.c. 2 59 CDC RID 3 58 RIC RXD 4 57 RXC VCC 5 56 GND INTSEL 6 55 TXRDY D0 7 54 RXRDY D1 8 53 RESET D2 9 52 n.c. 50 XTAL1 D4 12 49 n.c. D5 13 48 A0 D6 14 47 A1 D7 15 46 A2 n.c. 40 DSRB 39 CTSB 38 DTRB 37 GND 36 RTSB 35 INTB 34 CSB 33 TXB 32 IOW 31 n.c.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 37 GND 38 RXD 39 D0 40 D1 41 D2 42 D3 43 D4 44 D5 45 D6 46 D7 terminal 1 index area 47 GND 48 RXA 5.1.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 5.2 Pin description Table 2. Symbol Pin description Pin Type Description PLCC68 LQFP64 LQFP80 HVQFN48 16/68 31 - - 14 I 16/68 Interface type select (input with internal pull-up). This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of IOR, IOW, INTA to INTD, and CSA to CSD are re-assigned with the logic state of this pin.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description Clear to Send (active LOW). These inputs are associated with individual UART channels A to D. A logic 0 on the CTSn pin indicates the modem or data set is ready to accept transmit data from the SC16C554B/554DB. Status can be tested by reading MSR[4].
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description PLCC68 LQFP64 LQFP80 HVQFN48 INTSEL 65 - 6 - I Interrupt Select (active HIGH, with internal pull-down). This function is associated with the 16 mode only.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description PLCC68 LQFP64 LQFP80 HVQFN48 RESET (RESET) 37 27 53 20 I Reset. In the 16 mode, a logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.10 “SC16C554B/554DB external reset conditions” for initialization details.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description Transmit data A, B, C, D. These outputs are associated with individual serial transmit channel data from the SC16C554B/554DB. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6. Functional description The SC16C554B/554DB provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.1 Interface options Two user interface modes are selectable for the PLCC68 package. These interface modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature corresponds to the early 16C454/554 and 68C454/554 package interfaces respectively. 6.1.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.2 Internal registers The SC16C554B/554DB provides 12 internal registers for monitoring and control. These registers are shown in Table 5.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.4 Autoflow control (see Figure 9) Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Remark: Auto-CTS is not supported in channel D of the HVQFN48 package, therefore MCR[5] of channel D should not be written. 6.4.3 Enabling autoflow control and auto-CTS Autoflow control is enabled by setting MCR[5] and MCR[1]. Table 7. Enabling autoflow control and auto-CTS MCR[5] MCR[1] Selection 1 1 auto RTS and CTS 1 0 auto CTS 0 X disable 6.4.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs RX RTS byte 14 byte 15 Start byte 16 Stop Start byte 18 Stop RTS released after the first data bit of byte 16 IOR 002aaa051 (1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth byte.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for supporting a 5 Mbit/s data rate. The SC16C554B/554DB can be configured for internal or external clock operation.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.7 DMA operation The SC16C554B/554DB FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]).
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7. Register descriptions Table 9 details the assigned bit functions for the SC16C554B/554DB internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.10. Table 9.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the THR, providing that the THR or TSR is empty.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.3.2 FIFO mode Table 11. FIFO Control Register bits description Bit Symbol Description 7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 12.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 12. RCVR trigger levels FCR[7] FCR[6] RX FIFO trigger level 0 0 1 0 1 4 1 0 8 1 1 14 7.4 Interrupt Status Register (ISR) The SC16C554B/554DB provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15. Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 16. LCR[5] LCR[4] LCR[3] Parity selection X X 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity ‘1’ 1 1 1 forced parity ‘0’ Table 17. LCR[2] stop bit length LCR[2] Word length (bits) Stop bit length (bit times) 0 5, 6, 7, 8 1 1 5 11∨2 1 6, 7, 8 2 Table 18.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Modem Control Register bits description Bit Symbol Description 7:6 MCR[7:6] Reserved; set to ‘0’. 5 MCR[5] Autoflow control enable. 4 MCR[4] Loopback. Enable the local Loopback mode (diagnostics).
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C554B/554DB and the CPU. Table 20. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C554B/554DB is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.9 Scratchpad Register (SPR) The SC16C554B/554DB provides a temporary data register to store 8 bits of user information. 7.10 SC16C554B/554DB external reset conditions Table 22.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 9. Static characteristics Table 25. Static characteristics Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V VCC = 3.3 V VCC = 5.0 V Min Max Min Max Min Max Unit VIL(clk) clock LOW-level input voltage −0.3 +0.45 −0.3 +0.6 −0.5 +0.6 V VIH(clk) clock HIGH-level input voltage 1.8 VCC 2.4 VCC 3.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 10. Dynamic characteristics Table 26. Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V Min Max VCC = 3.3 V Min Max VCC = 5.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 26. Dynamic characteristics …continued Tamb = −40 °C to +85 °C; tolerance of VCC ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V VCC = 3.3 V VCC = 5.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs A0 to A4 t30s t30w t30h CS t32h t32s t32d R/W t33h t33s D0 to D7 002aaa211 Fig 19. General write timing in 68 mode t6h valid address A0 to A2 t13h t6s active CS t13d IOW t15d t13w active t16s D0 to D7 t16h data 002aaa171 Fig 20. General write timing in 16 mode SC16C554B_554DB Product data sheet All information provided in this document is subject to legal disclaimers. Rev.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs t6h valid address A0 to A2 t7h t6s active CS t7d t9d t7w IOR active t12h t12d D0 to D7 data 002aaa172 Fig 21.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs tWL tWH external clock tw(clk) 002aac357 1 f XTAL = --------------t w ( clk ) Fig 23. External clock timing start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits t20d active INT t21d active IOR 16 baud rate clock 002aaa113 Fig 24.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit D0 RX parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 t25d active data ready RXRDY t26d active IOR 002aab063 Fig 25.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit parity bit data bits (0 to 7) TX D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits active transmitter ready INT t22d t24d t23d IOW active active 16 baud rate clock 002aaa116 Fig 27.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit data bits (0 to 7) D0 TX parity bit D1 D2 D3 D4 D5 D6 stop bit D7 5 data bits 6 data bits 7 data bits IOW active t28d D0 to D7 byte #16 t27d TXRDY FIFO full 002aab061 Fig 29. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C554B_554DB Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 8 June 2010 © NXP B.V. 2010.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 11. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 1 detail X 20 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 c y X 48 A 33 49 32 ZE e A A2 E HE (A 3) A1 wM θ bp pin 1 index Lp L 64 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.15 0.05 1.45 1.35 0.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm A B D SOT778-3 terminal 1 index area E A A1 c detail X C e1 e v w b 1/2 e 13 M M y y1 C C A B C 24 L 25 12 e e2 Eh 1/2 e 1 terminal 1 index area 36 48 37 X Dh 0 2.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 E HE pin 1 index A e A4 A1 (A 3) β 9 Lp 27 k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A D(1) E(1) e HD A3 eD eE bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE k 23.62 23.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 12.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 14. Revision history Table 30. Revision history Document ID Release date SC16C554B_554DB v.4 20100608 Modifications: Data sheet status Supersedes Product data sheet SC16C554B_554DB_3 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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SC16C554B/554DB NXP Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 17. Contents 1 2 3 4 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2 6 6.1 6.1.1 6.1.2 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.6 6.7 6.8 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .