Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSC16C652BIB48,151

1. General description

The SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

The SC16C652B is pin compatible with the SC16C2550. It will power-up to be functionally

equivalent to the 16C2450. The SC16C652B provides enhanced UART functions with

32-byte FIFOs, modem control interface, DMA mode data transfer, and IrDA

encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger levels

and the TXRDY and RXRDY signals. On-board status registers provide the user with error

indications and operational status. System interrupts and modem control features may be

tailored by software to meet speciﬁc user requirements. An internal loop-back capability

allows on-board diagnostics. Independent programmable baud rate generators are

provided to select transmit and receive baud rates.

The SC16C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in plastic LQFP48 and very small (Micro-UART) HVQFN32 packages.

2. Features

■ 2 channel UART

■ 5 V, 3.3 V and 2.5 V operation

■ 5 V tolerant inputs

■ Industrial temperature range (−40 °C to +85 °C)

■ Pin and functionally compatible to 16C2450 in LQFP48 package, and software

compatible with industry standard 16C450, 16C550, and SC16C650

■ Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

■ 32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

■ 32-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

■ Independent transmit and receive UART control

■ Four selectable Receive and Transmit FIFO interrupt trigger levels

■ Automatic software (Xon/Xoff) and hardware (RTS/CTS) ﬂow control

■ Programmable Xon/Xoff characters

■ Software selectable baud rate generator

■ Standard modem interface or infrared IrDA encoder/decoder interface

■ Supports IrDA version 1.0 (up to 115.2 kbit/s)

■ Sleep mode

■ Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

SC16C652B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte

FIFOs and infrared (IrDA) encoder/decoder

Rev. 04 — 1 September 2005 Product data sheet

Summary of content (43 pages)

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SC16C652B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoder Rev. 04 — 1 September 2005 Product data sheet 1. General description The SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. The SC16C652B is pin compatible with the SC16C2550.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder ■ Transmit, Receive, Line Status, and Data Set interrupts independently controlled ■ Fully programmable character formatting: ◆ 5-bit, 6-bit, 7-bit, or 8-bit characters ◆ Even, odd, or no-parity formats ◆ 1, 11⁄2, or 2-stop bit ◆ Baud generation (DC to 5 Mbit/s) ■ False start-bit detection ■ Complete status reporting capabilities ■ 3-state output TTL drive capabilities for bi-directional data bus and control bus ■ Line
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 4.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 5. Pinning information 37 n.c. 38 CTSA 39 DSRA 40 CDA 42 VCC 41 RIA 43 TXRDYA 44 D0 45 D1 46 D2 47 D3 48 D4 5.1 Pinning D5 1 36 RESET D6 2 35 DTRB D7 3 34 DTRA RXB 4 33 RTSA RXA 5 32 OP2A TXRDYB 6 TXA 7 TXB 8 29 INTB OP2B 9 28 A0 CSA 10 27 A1 CSB 11 26 A2 n.c. 12 25 n.c. 31 RXRDYA n.c.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 5.2 Pin description Table 2: Pin description Symbol Pin Type Description LQFP48 HVQFN32 A0 28 19 I Address 0 select bit. Internal register address selection. A1 27 18 I Address 1 select bit. Internal register address selection. A2 26 17 I Address 2 select bit. Internal register address selection. CDA 40 - I CDB 16 - Carrier Detect (active LOW).
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Table 2: Pin description …continued Symbol Pin Type Description LQFP48 HVQFN32 IOW 15 12 I Write strobe (active LOW strobe). A logic 0 transition on this pin will transfer the contents of the data bus (D0 to D7) from the external CPU to an internal register that is defined by address bits A0 to A2. OP2A 32 22 O OP2B 9 7 Output 2 (user-defined).
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Table 2: Pin description …continued Symbol Pin Type Description LQFP48 HVQFN32 VCC 42 26 I Power supply input. XTAL1 13 10 I Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. This configuration requires an external 1 MΩ resistor between the XTAL1 and XTAL2 pins.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 6.1 UART A-B functions The UART provides the user with the capability to bi-directionally transfer information between an external CPU, the SC16C652B package, and an external serial device. A logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 3.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 6.3 FIFO operation The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger level, but not the transmit trigger level. The SC16C652B provides independent trigger levels for both receiver and transmitter. To remain compatible with SC16C2550, the transmit interrupt trigger level is set to 16 following a reset.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the Receive Holding Register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times. 6.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Table 6: Baud rate generator programming table using a 1.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the user data bus interface, D[7:0]. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface D[7:0].
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C652B UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set. Sleep mode is entered when: • • • • Modem input pins are not toggling. The serial data input line, RX, is idle (logic HIGH). The TX FIFO and TX shift register are empty. There are no interrupts pending.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7. Register descriptions Table 9 details the assigned bit functions for the SC16C652B internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the TSR and UART via the THR, providing that the THR is empty.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Table 10: Interrupt Enable Register bits description …continued Bit Symbol Description 1 IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will be issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO modes, this interrupt will be issued whenever the FIFO is empty.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit 3 = 0) Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Table 11: Bit FIFO Control Register bits description …continued Symbol 3 (cont.) Description Transmit operation in mode ‘1’: When the SC16C652B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 when the trigger level has been reached.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.4 Interrupt Status Register (ISR) The SC16C652B provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 16: Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced Feature mode enable.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 20: Modem Control Register bits description Bit Symbol Description 7 MCR[7] Clock select logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6] IR enable (see Figure 17).
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C652B and the CPU. Table 21: Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C652B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Software flow control functions [1] Table 24: Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls 0 0 X X No transmit flow control 1 0 X X Transmit Xon1/Xoff1 0 1 X X Transmit Xon2/Xoff2 1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2 X X 0 0 No receive flow control X X 1 0 Receiver compares Xon1/Xoff1 X X 0 1 Receiver compares Xon2/Xoff2 1 0 1 1 Transmit Xon1/Xoff1 Rec
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 8. Limiting values Table 27: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions Min Max Unit - 7 V GND − 0.3 VCC + 0.3 V −40 +85 °C Vn voltage at any pin Tamb ambient temperature Tstg storage temperature −65 +150 °C Ptot(pack) total power dissipation per package - 500 mW operating in free air 9.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 10. Dynamic characteristics Table 29: Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %; unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V Min t1w, t2w clock pulse duration fXTAL oscillator/clock frequency t6s VCC = 3.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder Table 29: Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %; unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V Min t28d delay from start to reset TXRDY tRESET RESET pulse width N [3] baud rate divisor VCC = 3.3 V Max Min VCC = 5.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder t6h valid address A0 to A2 t7h t6s active CSx t7d IOR t9d t7w active t12h t12d D0 to D7 data 002aaa110 Fig 7. General read timing IOW active t17d RTS DTR change of state change of state CD CTS DSR change of state change of state t18d INT t18d active active active t19d IOR active active active t18d change of state RI 002aaa352 Fig 8.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder t2w t1w EXTERNAL CLOCK 002aaa112 t3w 1 f XTAL = ------t 3w Fig 9. External clock timing start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits t20d active INT t21d active IOR 16 baud rate clock 002aaa113 Fig 10. Receive timing SC16C652B_4 Product data sheet © Koninklijke Philips Electronics N.V. 2005.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder start bit D0 RX parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 t25d active data ready RXRDY t26d active IOR 002aab063 Fig 11. Receive ready timing in non-FIFO mode start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit D7 first byte that reaches the trigger level t25d active data ready RXRDY t26d active IOR 002aab064 Fig 12.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder start bit parity bit data bits (0 to 7) TX D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits 7 data bits active transmitter ready INT t22d t24d t23d IOW active active 16 baud rate clock 002aaa116 Fig 13.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder start bit data bits (0 to 7) D0 TX parity bit D1 D2 D3 D4 D5 D6 stop bit D7 5 data bits 6 data bits 7 data bits IOW active t28d D0 to D7 byte #32 t27d TXRDY FIFO full 002aab065 Fig 15. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C652B_4 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder UART frame start data bits 0 TX data 1 0 1 0 stop 0 1 1 0 1 IrDA TX data 1/ bit time 2 bit time 3/ bit time 16 002aaa212 Fig 16. Infrared transmit timing IrDA RX data bit time RX data 0 to 1 16× clock delay 0 1 0 1 start 0 0 data bits 1 1 0 1 stop UART frame 002aaa213 Fig 17. Infrared receive timing SC16C652B_4 Product data sheet © Koninklijke Philips Electronics N.V. 2005.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e 16 y y1 C v M C A B w M C b 9 L 17 8 e e2 Eh 1/2 e 1 terminal 1 index area 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 14. Revision history Table 32: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes SC16C652B_4 20050901 Product data sheet - - SC16C652B-03 Modifications: • The format of this data sheet has be redesigned to comply with the new presentation and information standard of Philips Semiconductors.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification.
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SC16C652B Philips Semiconductors Dual UART with 32-byte FIFOs and IrDA encoder/decoder 20. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . .