Datasheet

9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 10 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5.2 Pin description
Table 2: Pin description
Symbol Pin Type Description
PLCC68 LQFP64 HVQFN48 LFBGA6
4
16/
68 31 - 14 - I 16/68 Interface type select (input with internal pull-up).
This input provides the 16 (Intel) or 68 (Motorola) bus
interface type select. The functions of
IOR, IOW,
INTA to INTD, and
CSA to CSD are re-assigned with the
logical state of this pin. When this pin is a logic 1, the
16 mode interface (16C654) is selected. When this pin is a
logic 0, the 68 mode interface (68C654) is selected. When
this pin is a logic 0,
IOW is re-assigned to R/W, RESET is
re-assigned to
RESET, IOR is not used, and INTA to INTD
are connected in a wire-OR configuration. The wire-OR
outputs are connected internally to the open-drain IRQ
signal output. This pin is not available on 64-pin packages
which operate in the 16 mode only.
A0 34 24 17 K5 I Address 0 select bit. Internal registers address selection in
16 and 68 modes.
A1 33 23 16 J5 I Address 1 select bit. Internal registers address selection in
16 and 68 modes.
A2 32 22 15 K4 I Address 2 select bit. Internal registers address selection in
16 and 68 modes.
A3 20 - 9 - I Address 3, Address 4 select bits. When the 68 mode is
selected, these pins are used to address or select individual
UARTs (providing
CS is a logic 0). In the 16 mode, these
pins are re-assigned as chip selects, see
CSB and CSC.
These pins are not available on 64-pin packages which
operate in the 16 mode only.
A4 50 - 31 -
CDA9 64 - A1 ICarrier Detect (active LOW). These inputs are associated
with individual UART channels A through D. A logic 0 on this
pin indicates that a carrier has been detected by the modem
for that channel.
CDB 27 18 - K2
CDC 43 31 24 J9
CDD 61 49 - A10
CLKSEL 30 - - - I Clock Select. The 1× or 4× pre-scalable clock is selected by
this pin. The 1× clock is selected when CLKSEL is a logic 1
(connected to V
CC
) or the 4× is selected when CLKSEL is a
logic 0 (connected to GND). MCR[7] can override the state
of this pin following reset or initialization (see MCR[7]). This
pin is not available on 64-pin packages which provide
MCR[7] selection only.
CS 16 - 5 - I Chip Select (active LOW). In the 68 mode, this pin
functions as a multiple channel chip enable. In this case, all
four UARTs (A to D) are enabled when the
CS pin is a
logic 0. An individual UART channel is selected by the data
contents of address bits A[3:4]. when the 16 mode is
selected (68-pin devices), this pin functions as
CSA (see
definition under
CSA, CSB). This pin is not available on
64-pin packages which operate in the 16 mode only.