Datasheet

9397 750 14965 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 02 — 20 June 2005 13 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
RIA 8 63 - A2 I Ring Indicator (active LOW). These inputs are associated
with individual UART channels, A through D. A logic 0 on this
pin indicates the modem has received a ringing signal from
the telephone line. A logic 1 transition on this input pin will
generate an interrupt.
RIB 28 19 - J3
RIC 42 30 23 K8
RID 62 50 - A9
RTSA 14 5 3 C2 O Request to Send (active LOW). These outputs are
associated with individual UART channels, A through D. A
logic 0 on the
RTS pin indicates the transmitter has data
ready and waiting to send. Writing a logic 1 in the modem
control register MCR[1] will set this pin to a logic 0,
indicating data is available. After a reset this pin will be set to
a logic 1. This pin only affects the transmit and receive
operations when Auto RTS function is enabled via the
Enhanced Feature Register (EFR[6]) for hardware flow
control operation.
RTSB 22 13 11 H2
RTSC 48 36 29 H9
RTSD 56 44 - C10
R/
W18 - 7 - IRead/Write strobe. This function is associated with the
68 mode only. This pin provides the combined functions for
Read or Write strobes.
Logic 1 = Read from UART register selected by CS and
A[0:4].
Logic 0 = Write to UART register selected by
CS and A[0:4].
RXA 7 62 48 A3 I Receive data input RXA-RXD. These inputs are associated
with individual serial channel data to the
SC16C654B/654DB. The RX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled.
During the local loop-back mode, the RX input pin is
disabled and TX data is connected to the UART RX input
internally.
RXB 29 20 13 K3
RXC 41 29 22 J8
RXD 63 51 38 B8
RXRDY38 - - - O Receive Ready (active LOW). This function is associated
with 68-pin package only.
RXRDY contains the wire-ORed
status of all four receive channel FIFOs, RXRDYA-RXRDYD.
A logic 0 indicates receive data ready status, that is, the
RHR is full, or the FIFO has one or more RX characters
available for unloading. This pin goes to a logic 1 when the
FIFO/RHR is empty, or when there are no more characters
available in either the FIFO or RHR. Individual channel RX
status is read by examining individual internal registers via
CS and A[0:4] pin functions.
TXA 17 8 6 E2 O Transmit data A, B, C, D. These outputs are associated
with individual serial transmit channel data from the
SC16C654B/654DB. The TX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled.
During the local loop-back mode, the TX output pin is
disabled and TX data is internally connected to the UART
RX input.
TXB 19 10 8 F2
TXC 51 39 32 F10
TXD 53 41 34 E10
Table 2: Pin description
…continued
Symbol Pin Type Description
PLCC68 LQFP64 HVQFN48 LFBGA6
4