SC16C654B/654DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder Rev. 02 — 20 June 2005 Product data sheet 1. General description The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter (QUART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. It comes with an Intel or Motorola interface.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 4.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 5. Pinning information D3 1 61 CDD D4 2 62 RID D5 3 63 RXD D6 4 64 VCC D7 5 65 INTSEL GND 6 66 D0 RXA 7 67 D1 RIA 8 68 D2 CDA 9 5.
SC16C654B/654DB Philips Semiconductors D3 1 61 CDD D4 2 62 RID D5 3 63 RXD D6 4 64 VCC D7 5 65 n.c. GND 6 66 D0 RXA 7 67 D1 RIA 8 68 D2 CDA 9 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 10 60 DSRD CTSA 11 59 CTSD DTRA 12 58 DTRD VCC 13 57 GND RTSA 14 56 RTSD IRQ 15 55 n.c. CS 16 54 n.c. TXA 17 53 TXD SC16C654BIA68 68 mode R/W 18 TXB 19 52 n.c. 51 TXC A3 20 50 A4 n.c. 21 49 n.c.
SC16C654B/654DB Philips Semiconductors 49 CDD 50 RID 51 RXD 52 VCC 53 D0 54 D1 55 D2 56 D3 57 D4 58 D5 59 D6 60 D7 61 GND 62 RXA 63 RIA 64 CDA 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
SC16C654B/654DB Philips Semiconductors 37 GND 38 RXD 39 D0 40 D1 41 D2 42 D3 43 D4 44 D5 45 D6 46 D7 terminal 1 index area 47 GND 48 RXA 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs ball A1 index area SC16C654BIEC 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aab566 Transparent top view Fig 8.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 5.2 Pin description Table 2: Pin description Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 16/68 31 - 14 - I 16/68 Interface type select (input with internal pull-up). This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of IOR, IOW, INTA to INTD, and CSA to CSD are re-assigned with the logical state of this pin.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 CSA 16 7 5 E1 CSB 20 11 9 G1 CSC 50 38 31 G9 CSD 54 42 35 E9 CTSA 11 2 1 C1 CTSB 25 16 12 J2 CTSC 45 33 26 K10 CTSD 59 47 - B10 I Chip Select A, B, C, D (active LOW). This function is associated with the 16 mode only, and for individual channels ‘A’ through ‘D’.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 INTSEL 65 - - - I Interrupt Select (active HIGH, with internal pull-down). This function is associated with the 16 mode only.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 RIA 8 63 - A2 RIB 28 19 - J3 RIC 42 30 23 K8 RID 62 50 - A9 RTSA 14 5 3 C2 RTSB 22 13 11 H2 RTSC 48 36 29 H9 RTSD 56 44 - C10 R/W 18 - 7 - I Ring Indicator (active LOW). These inputs are associated with individual UART channels, A through D.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 2: Pin description …continued Symbol Pin Type Description PLCC68 LQFP64 HVQFN48 LFBGA6 4 TXRDY 39 - - - O Transmit Ready (active LOW). This function is associated with the 68-pin package only. TXRDY contains the wire-ORed status of all four transmit channel FIFOs, TXRDYA-TXRDYD.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs time. In addition, the four selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance, especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.1 Interface options Two user interface modes are selectable for the PLCC68 package. These interface modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature corresponds to the early 16C454/554 and 68C454/554 package interfaces respectively. 6.1.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.2 Internal registers The SC16C654B/654DB provides 17 internal registers for monitoring and control. These registers are shown in Table 5. Twelve registers are similar to those already available in the standard 16C554.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. (For a description of this timing, see Section 6.4 “Hardware flow control”.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff characters and suspend/resume transmissions.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs SC16C654B/654DB sets the default baud rate table according to the state of the CLKSEL pin. A logic 1 on CLKSEL will set the 1× clock default, whereas logic 0 will set the 4× clock default table. Following the default clock rate selection during initialization, the rate tables can be changed by the internal register MCR[7].
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 6.10 DMA operation The SC16C654B/654DB FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[5:6] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]).
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7. Register descriptions Table 8 details the assigned bit functions for the SC16C654B/654DB internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the THR, providing that the THR or TSR is empty.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 9: Interrupt Enable Register bits description …continued Bit Symbol Description 2 IER[2] Receive Line Status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the THR is empty, and is associated with LSR[1].
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit 3 = 0) Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C454 mode.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 10: FIFO Control Register bits description …continued Bit Symbol Description 3 (cont.) FCR[3] (continued) Transmit operation in mode ‘1’: When the SC16C654B/654DB is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 when the trigger level has been reached.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.4 Interrupt Status Register (ISR) The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15: Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 19: Modem Control Register bits description …continued Bit Symbol Description 4 MCR[4] Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C654B/654DB I/O pins.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C654B/654DB and the CPU. Table 20: Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C654B/654DB is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 7.9 Scratchpad Register (SPR) The SC16C654B/654DB provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 8. Limiting values Table 26: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VCC supply voltage Max Unit - 7 V Vn voltage at any pin GND − 0.3 VCC + 0.
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SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 10. Dynamic characteristics Table 28: Dynamic characteristics Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V Min t1w, t2w clock pulse duration fXTAL oscillator/clock frequency t6s VCC = 3.3 V Max Min VCC = 5.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Table 28: Dynamic characteristics …continued Tamb = −40 °C to +85 °C; tolerance of VCC = ± 10 %, unless otherwise specified. Symbol Parameter Conditions VCC = 2.5 V Min t28d delay from start to reset TXRDY - Max 8TRCLK Min - [3] address setup time t30s VCC = 3.3 V [1] 25 pF load VCC = 5.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 10.1 Timing diagrams A0 to A4 t30s t30h t30w t30d CS t31h t32s R/W t31d D0 to D7 002aaa210 Fig 13. General read timing in 68 mode A0 to A4 t30s t30w t30h CS t32s t32h t32d R/W t33s t33h D0 to D7 002aaa211 Fig 14. General write timing in 68 mode 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs t6h valid address A0 to A2 t13h t6s active CS t13d t15d t13w IOW active t16s D0 to D7 t16h data 002aaa171 Fig 15. General write timing in 16 mode t6h valid address A0 to A2 t7h t6s active CS t7d t9d t7w IOR active t12h t12d D0 to D7 data 002aaa172 Fig 16. General read timing in 16 mode 9397 750 14965 Product data sheet © Koninklijke Philips Electronics N.V. 2005.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs active IOW t17d RTS DTR change of state change of state CD CTS DSR change of state t18d INT change of state t18d active active active t19d active IOR active active t18d change of state RI 002aaa352 Fig 17. Modem input/output timing t2w t1w EXTERNAL CLOCK 002aaa112 t3w 1 f XTAL = ------t 3w Fig 18.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit RX parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits t20d 7 data bits active INT t21d active IOR 16 baud rate clock 002aaa113 Fig 19.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit D0 RX parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit D7 first byte that reaches the trigger level t25d active data ready RXRDY t26d active IOR 002aab064 Fig 21.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs start bit D0 TX IOW parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 active t28d D0 to D7 byte #1 t27d TXRDY active transmitter ready transmitter not ready 002aab062 Fig 23.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs UART frame start data bits 0 TX data 1 0 1 0 stop 0 1 1 0 1 IrDA TX data 1/ bit time 2 bit time 3/ bit time 16 002aaa212 Fig 25. Infrared transmit timing IrDA RX data bit time RX data 0 to 1 16× clock delay 0 1 0 1 start 0 0 data bits 1 1 0 1 stop UART frame 002aaa213 Fig 26.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 11. Package outline PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 E HE pin 1 index A e A4 A1 (A 3) β 9 Lp 27 k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A D(1) E(1) e A3 eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 c y X 48 A 33 49 32 ZE e A A2 E HE (A 3) A1 wM θ bp pin 1 index Lp L 64 17 1 detail X 16 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.15 0.05 1.45 1.35 0.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm A B D SOT778-3 terminal 1 index area E A A1 c detail X C e1 e v w b 1/2 e 13 M M y1 C C A B C y 24 L 25 12 e e2 Eh 1/2 e 1 terminal 1 index area 36 48 37 X Dh 0 2.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 6 x 6 x 1.05 mm D SOT686-1 A B ball A1 index area A A2 E A1 detail X e1 C e 1/2 e y y1 C ∅v M C A B b ∅w M C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 14. Revision history Table 31: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes SC16C654B_654DB_2 20050620 Product data sheet - 9397 750 14965 SC16C654B_654DB_1 Modifications: • Section 1 “General description”: – 2nd paragraph: added 6th sentence. – 3rd paragraph: added HVQFN48 and LFBGA64 package options, and added second sentence.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.
SC16C654B/654DB Philips Semiconductors 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 20. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . .