SC16C752B 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 6 — 30 November 2010 Product data sheet 1. General description The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 4.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 5. Pinning information 37 n.c. 38 CTSA 39 DSRA 40 CDA 41 RIA 42 VCC 43 TXRDYA 44 D0 45 D1 46 D2 D5 1 36 RESET D6 2 35 DTRB D7 3 34 DTRA RXB 4 33 RTSA RXA 5 32 OPA TXRDYB 6 TXA 7 TXB 8 29 INTB OPB 9 28 A0 CSA 10 27 A1 CSB 11 26 A2 n.c. 12 25 n.c. 31 RXRDYA n.c.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 5.2 Pin description Table 2. Symbol Pin description Pin Type Description I Address 0 select bit. Internal registers address selection. LQFP48 HVQFN32 A0 28 19 A1 27 18 I Address 1 select bit. Internal registers address selection. A2 26 17 I Address 2 select bit. Internal registers address selection. CDA 40 - I CDB 16 - i Carrier Detect (active LOW).
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 2. Symbol Pin description …continued Pin Type Description LQFP48 HVQFN32 IOW 15 12 I Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on IOW will transfer the contents of the data bus (D0 to D7) from the external CPU to an internal register that is defined by address bits A0 to A2 and CSA and CSB. n.c.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6. Functional description The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides more enhanced features. All additional features are provided through a special Enhanced Feature Register (EFR). The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs UART 1 UART 2 SERIAL TO PARALLEL RXn PARALLEL TO SERIAL TXn RX FIFO TX FIFO FLOW CONTROL RTSn CTSn FLOW CONTROL D7 to D0 D7 to D0 PARALLEL TO SERIAL TXn SERIAL TO PARALLEL RXn TX FIFO RX FIFO FLOW CONTROL RTSn CTSn FLOW CONTROL 002aaf905 Fig 4. Auto flow control (auto-RTS and auto-CTS) example 6.2.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.2.2 Auto-CTS The transmitter circuitry checks CTSn before sending the next data byte. When CTSn is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTSn must be de-asserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Operation will resume after receiving any character after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the receive FIFO. • Special character (EFR[5]): Incoming data is compared to Xoff2.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.3.3 Software flow control example UART1 UART2 TRANSMIT FIFO PARALLEL-TO-SERIAL RECEIVE FIFO data SERIAL-TO-PARALLEL Xoff–Xon–Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon1 WORD Xon1 WORD Xon2 WORD Xon2 WORD Xoff1 WORD Xoff1 WORD Xoff2 WORD Fig 7. 6.3.3.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.4 Reset Table 4 summarizes the state of register after reset. Table 4.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.5 Interrupts The SC16C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the INTA/INTB signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bit 0 to bit 3 and bit 5 to bit 7.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INTA/INTB. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 8 shows interrupt mode operation.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. 6.6.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.6.2 Block DMA transfers (DMA mode 1) Figure 11 shows TXRDYn and RXRDYn in DMA mode 1. transmit wrptr receive trigger level TXRDYn RXRDYn rdptr at least one location filled FIFO full trigger level TXRDYn wrptr RXRDYn rdptr FIFO EMPTY 002aaa234 Fig 11. TXRDYn and RXRDYn in DMA mode 1 6.6.2.1 Transmitter TXRDYn is active when there is a trigger level number of spaces available.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RXn, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TXn line is pulled LOW. A break condition is activated by setting LCR[6]. 6.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 7. Desired baud rate Divisor used to generate 16× clock 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 Table 8. SC16C752B Product data sheet Baud rates using a 1.8432 MHz crystal Percent error difference between desired and actual 0.69 2.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs XTAL1 XTAL2 XTAL1 X1 1.8432 MHz XTAL2 X1 1.8432 MHz C1 22 pF C2 33 pF C1 22 pF 1.5 kΩ C2 47 pF 002aaa870 Fig 13. Crystal oscillator connections 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9. Table 9.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 10 lists and describes the SC16C752B internal registers. Table 10.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Remark: Refer to the notes under Table 9 for more register access information. 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11 shows FIFO control register bit settings. Table 11. FIFO Control Register bits description Bit Symbol Description 7:6 FCR[7] (MSB), RX trigger.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the Line Control Register bit settings. Table 12. Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.5 Line Status Register (LSR) Table 13 shows the Line Status Register bit settings. Table 13. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = At least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 14 shows modem control register bit settings. Table 14. Modem Control Register bits description Bit Symbol Description 7 MCR[7][1] Clock select. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6][1] TCR and TLR enable.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 15 shows Modem Status Register bit settings per channel. Table 15. Bit Symbol Description 7 MSR[7] CD (active HIGH, logic 1)[1].
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTSn/RTSn change of state from LOW to HIGH. The INTA/INTB output signal is activated in response to interrupt generation. Table 16 shows Interrupt Enable Register bit settings. Table 16.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17 shows Interrupt Identification Register bit settings. Table 17.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 19. Enhanced Feature Register bits description …continued Bit Symbol Description 5 EFR[5] Special character detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. Received data is compared with Xoff2 data.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.13 Trigger Level Register (TLR) This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 21 shows trigger level register bit settings. Table 21.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 8. Programmer’s guide The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 23.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 9. Limiting values Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VCC supply voltage Vn voltage on any other pin Tamb ambient temperature Tstg storage temperature Min Max Unit - 7 V at D7 to D0 pins GND − 0.3 VCC + 0.3 V at any input only pin GND − 0.3 5.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs [5] Except XTAL2, VOL = 1 V typical. [6] These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 °C. The customer is responsible for verifying junction temperature. [7] Measurement condition, normal operation other than Sleep mode: VCC = 3.3 V; Tamb = 25 °C.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 26. Dynamic characteristics …continued Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %, unless specified otherwise. Symbol Parameter Conditions VCC = 2.5 V VCC = 3.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs valid address A0 to A2 tsu1 th4 active CSA, CSB td5 th2 tw2 IOW td6 active tsu2 D0 to D7 th3 data 002aaa236 Fig 15.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit RXA, RXB parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 Stop bit next data Start bit D7 5 data bits 6 data bits td10 7 data bits active INTA, INTB td11 active IOR 16 baud rate clock 002aaa239 Fig 17.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs start bit parity bit data bits (0 to 7) D0 RXA, RXB D1 D2 D3 D4 D5 D6 stop bit D7 first byte that reaches the trigger level td15 active data ready RXRDYA RXRDYB td16 active IOR 002aaa241 Fig 19.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs start bit TXA, TXB D0 IOW active D0 to D7 byte #1 parity bit data bits (0 to 7) D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 td18 td17 TXRDYA TXRDYB active transmitter ready transmitter not ready 002aaa243 Fig 21.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e b 9 y y1 C v M C A B w M C 16 L 17 8 e e2 Eh 1/2 1 terminal 1 index area e 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 13.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 29.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
SC16C752B NXP Semiconductors 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 6.7 6.8 6.9 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . .