SC16C852SV 1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface Rev. 01 — 23 September 2008 Product data sheet 1. General description The SC16C852SV is a 1.8 V, low power dual channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 20 Mbit/s (4× sampling rate).
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface n n n n n n n n n Industrial temperature range (−40 °C to +85 °C) Software compatible with industry standard SC16C652B Software selectable baud rate generator Supports IrDA version 1.0 (up to 115.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 4.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 5. Pinning information 5.1 Pinning SC16C852SVIET ball A1 index area 1 2 3 4 5 6 A B C D E F 002aad603 Transparent top view Fig 2.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Table 2. Pin description …continued Symbol Pin Type Description CS E2 I Chip Select (active LOW). This pin enables the data transfers between the host and the SC16C852SV for the addressed channel. Individual channel selection is done with address A6. When A6 is 0 channel A is selected, and when A6 is 1 channel B is selected. CTSA A6 I CTSB F6 Clear to Send (active LOW).
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Table 2. Pin description …continued Symbol Pin Type Description RESET B5 I Master reset (active LOW). A reset pulse will reset the internal registers and all the outputs. The SC16C852SV transmitter outputs and receiver inputs will be disabled during reset time. (See Section 7.24 “SC16C852SV external reset condition and software reset” for initialization details.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 6. Functional description The SC16C852SV provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL. 6.3 Internal registers The SC16C852SV provides two sets of internal registers (A and B) consisting of 25 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface [1] These registers are accessible only when LCR[7] is a logic 0. [2] These registers are accessible only when LCR[7] is a logic 1. [3] Second special register are accessible only when EFCR[0] = 1. [4] Enhanced feature registers are only accessible when LCR = 0xBF. [5] First extra feature registers are only accessible when EFCR[2:1] = 01b.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface SC16C852SV will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTSx input returns to a logic 0, indicating more data may be sent. When AFCR1[2] is set to 1, then the function of CTSx pin is mapped to the DSRx pin, and the function of RTS is mapped to DTRx pin. DSRx and DTRx pins will behave as described above for CTSx and RTSx.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters cannot be used for data transfer. In the event that the receive buffer is overfilling, the SC16C852SV automatically sends an Xoff character (when enabled) via the serial TX output to the remote UART.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 6.9 Programmable baud rate generator The SC16C852SV UART contains a programmable rational baud rate generator that takes any clock input and divides it by a divisor in the range between 1 and (216 − 1). The SC16C852SV offers the capability of dividing the input frequency by rational divisor. The fractional part of the divisor is controlled by the CLKPRES register in the First Extra Register Set.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface However, the user can also select 4×, 8× sampling rates (see Section 7.20 “Sampling Rate (SAMPR)”) to operate at four times or two times faster than 16× sampling rate. Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 6 shows the selectable baud rate table available when using a 1.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Table 6. Baud rate generator programming table using a 1.8432 MHz clock with MCR[7] = 0, SAMPR[1:0] = 00b and CLKPRE[3:0] = 0 …continued Output baud rate (bit/s) Output 16× clock divisor (decimal) Output 16× clock divisor (hexadecimal) DLM program value (hexadecimal) DLL program value (hexadecimal) 19.2 k 6 06 00 06 38.4 k 3 03 00 03 57.6 k 2 02 00 02 115.2 k 1 01 00 01 6.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface SC16C852SV AD0 to AD7 IOR IOW RESET LLA TRANSMIT FIFO REGISTER TRANSMIT SHIFT REGISTER TXA, TXB DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC IR ENCODER CS REGISTER SELECT LOGIC INTERCONNECT BUS LINES AND CONTROL SIGNALS MCR[4] = 1 RECEIVE FIFO REGISTER FLOW CONTROL LOGIC RECEIVE SHIFT REGISTER RXA, RXB IR DECODER RTSA, RTSB LOWPWR POWER DOWN CONTROL CTSA, CTSB MODEM CONTROL LOGIC DTRA, DT
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C852SV UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] of both channels are set. 6.11.1 Conditions to enter Sleep mode Sleep mode is entered when: • Modem input pins are not toggling. • The serial data input line, RXA/RXB, is idle for 4 character time (logic HIGH) and AFCR1[4] is 0.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 6.13 RS-485 features 6.13.1 Auto RS-485 RTS control Normally the RTSx pin is controlled by MCR bit 1, or if hardware flow control is enabled, the logic state of the RTSx pin is controlled by the hardware flow control circuitry. EFCR2 register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTSx pin.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 6.13.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the address byte), the receiver will try to detect an address byte that matches the programmed character in the XOFF2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard these data.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx A3 A2 NXP Semiconductors SC16C852SV_1 Product data sheet Table 7.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx A3 A2 SC16C852SV internal registers …continued A1 Register Enhanced register Default[1] Bit 7 Bit 6 B
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (AD7 to AD0) to the transmit FIFO.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Table 8. Interrupt Enable Register bits description …continued Bit Symbol Description 1 IER[1] Transmit Holding Register interrupt. In the non-FIFO mode, this interrupt will be issued whenever the THR is empty, and is associated with LSR[5]. In the FIFO modes, this interrupt will be issued whenever the FIFO is empty.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger levels. 7.3.1 FIFO mode Table 9. FIFO Control Register bits description Bit Symbol Description 7:6 FCR[7:6] Receive trigger level in 32-byte FIFO mode.[1] These bits are used to set the trigger level for receive FIFO interrupt and flow control.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Table 10. RCVR trigger levels FCR[7] FCR[6] RX FIFO trigger level in 32-byte FIFO mode[1] 0 0 8 bytes 0 1 16 bytes 1 0 24 bytes 1 1 28 bytes [1] When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “FIFO operation”. Table 11.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.4 Interrupt Status Register (ISR) The SC16C852SV provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 14. Line Control Register bits description Bit Symbol Description 7 LCR[7] Divisor latch enable.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 18. Modem Control Register bits description Bit Symbol Description 7 MCR[7] Clock select logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6] IR enable (see Figure 15).
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C852SV and the CPU. Table 20. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current FIFO data.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C852SV is connected. Four bits of this register are used to indicate the changed information.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: First Extra Register Set, Second Extra Register Set, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT). Table 22.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0 through bit 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential numbers. Table 23.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Software flow control functions[1] …continued Table 24.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. Table 27 shows transmission control register bit settings; see Section 6.5. Table 27.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.20 Sampling Rate (SAMPR) Bit 1 and bit 0 of this register program the device’s sampling rate. Table 30. Sampling rate Bit Symbol Description 7:2 SAMPR[7:2] reserved 1:0 SAMPR[1:0] sampling rate 00 = 16× 01 = 8× 10 = 4× 11 = reserved 7.21 RS-485 turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface Table 32. Advanced Feature Control Register 1 bits description …continued Bit Symbol Description 1 AFCR1[1] SReset. Software reset. A write to this bit will reset the UART. Once the UART is reset this bit is automatically set to 0.[1] 0 AFCR1[0] TSR interrupt. Select TSR interrupt mode. 0 = transmit empty interrupt occurs when transmit FIFO falls below the trigger level or becomes empty.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 7.24 SC16C852SV external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 34. Table 34.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 8. Limiting values Table 36. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage Vn voltage on any other pin Tamb ambient temperature Tstg storage temperature [1] operating in free air Ptot/pack total power dissipation per package [1] Min Max Unit - 2.5 V VSS − 0.3 VDD + 0.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 10. Dynamic characteristics Table 38. Dynamic characteristics Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise specified.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 10.1 Timing diagrams AD7 to AD0 upper address lower address tsu(A-LLAH) data th(LLAH-A) CS td(CS-LLAH) th(IOWH-D) tw(LLA) LLA tsu(D-IOWH) td(LLAH-IOWL) tw(IOW) td(IOW) IOW 002aac354 Fig 8. General write timing AD7 to AD0 upper address lower address tsu(A-LLAH) data th(LLAH-A) tdis(IOR-QZ) CS td(CS-LLAH) tw(LLA) LLA td(IOR-DV) td(IOR) td(LLAH-IORL) tw(IOR) IOR 002aac355 Fig 9.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface active IOW td(IOW-Q) RTSA, RTSB DTRA, DTRB change of state change of state CDA, CDB CTSA, CTSB DSRA, DSRB change of state td(modem-INT) INTA, INTB change of state td(modem-INT) active active active td(IOR-INTL) active IOR active active td(modem-INT) change of state RIA, RIB 002aac356 Fig 10.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface start bit RXA, RXB parity bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 stop bit next data start bit D7 5 data bits 6 data bits td(stop-INT) 7 data bits active INTA, INTB td(IOR-INTL) active IOR sampling rate × baud rate clock 002aad605 Fig 12.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface UART frame start data bits 0 TX data 1 0 1 0 stop 0 1 1 0 1 IrDA TX data 1/ bit time 2 bit time 3/ bit time 16 002aaa212 Fig 14. Infrared transmit timing IrDA RX data bit time RX data 0 to 1 16× clock delay 0 1 0 1 start 0 0 data bits 1 1 0 1 stop UART frame 002aaa213 Fig 15. Infrared receive timing SC16C852SV_1 Product data sheet © NXP B.V. 2008. All rights reserved.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 11. Package outline TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm B D SOT912-1 A ball A1 index area E A A2 A1 detail X e1 1/2 e e v w b F M M C C A B C y1 C y e E D e2 C B 1/2 e A ball A1 index area 1 2 3 4 5 6 X 0 2.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 12.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 41.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
SC16C852SV NXP Semiconductors Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . .