Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSC16IS741IPW,112

1. General description

The SC16IS741 is a slave I

C-bus/SPI interface to a single-channel high performance

UART. It offers data rates up to 5 Mbit/s and guarantees low operating and sleeping

current. The device comes in the TSSOP16 package, which makes it ideally suitable for

handheld, battery operated applications. This device enables seamless protocol

conversion from I

C-bus or SPI to and RS-232/RS-485 and are fully bidirectional.

The SC16IS741’s internal register set is backward-compatible with the widely used and

widely popular 16C450. This allows the software to be easily written or ported from

another platform.

The SC16IS741 also provides additional advanced features such as auto hardware and

software flow control, automatic RS-485 support, and software reset. This allows the

software to reset the UART at any moment, independent of the hardware reset signal.

2. Features

2.1 General features

 Single full-duplex UART

 Selectable I

C-bus or SPI interface

 3.3 V or 2.5 V operation

 Industrial temperature range: −40 °C to +95 °C

 64 bytes FIFO (transmitter and receiver)

 Fully compatible with industrial standard 16C450 and equivalent

 Baud rates up to 5 Mbit/s in 16× clock mode

 Auto hardware flow control using RTS

/CTS

 Auto software flow control with programmable Xon/Xoff characters

 Single or double Xon/Xoff characters

 Automatic RS-485 support (automatic slave address detection)

 RS-485 driver direction control via RTS

signal

 RS-485 driver direction control inversion

 Built-in IrDA encoder and decoder interface

 Software reset

 Transmitter and receiver can be enabled/disabled independent of each other

 Receive and Transmit FIFO levels

 Programmable special character detection

SC16IS741

Single UART with I

C-bus/SPI interface, 64 bytes of transmit

and receive FIFOs, IrDA SIR built-in support

Rev. 01 — 29 April 2010 Product data sheet

Summary of content (52 pages)

PAGE 1
SC16IS741 Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 01 — 29 April 2010 Product data sheet 1. General description The SC16IS741 is a slave I2C-bus/SPI interface to a single-channel high performance UART. It offers data rates up to 5 Mbit/s and guarantees low operating and sleeping current. The device comes in the TSSOP16 package, which makes it ideally suitable for handheld, battery operated applications.
PAGE 2
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Fully programmable character formatting 5-bit, 6-bit, 7-bit or 8-bit character Even, odd, or no parity 1, 11⁄2, or 2 stop bits Line break generation and detection Internal Loopback mode Sleep current less than 30 μA at 3.3 V Industrial and commercial temperature ranges Available in the TSSOP16 package 2.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 5. Block diagram VDD SC16IS741 RESET SCL 16C450 COMPATIBLE REGISTER SETS SDA A0 I2C-BUS A1 TX RX RTS CTS IRQ 1 kΩ (3.3 V) 1.5 kΩ (2.5 V) VDD VDD I2C/SPI XTAL1 Fig 1. XTAL2 VSS 002aaf155 Block diagram of SC16IS741 I2C-bus interface VDD SC16IS741 RESET SCLK 16C450 COMPATIBLE REGISTER SETS CS SO SPI SI TX RX RTS CTS IRQ 1 kΩ (3.3 V) 1.5 kΩ (2.5 V) VDD I2C/SPI XTAL1 Fig 2.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 6. Pinning information 6.1 Pinning VDD 1 16 XTAL2 VDD 1 16 XTAL2 A0 2 15 XTAL1 CS 2 15 XTAL1 A1 3 14 RESET SI 3 14 RESET n.c. 4 13 RX SO 4 SCL 5 12 TX SCLK 5 SDA 6 11 CTS VSS 6 11 CTS IRQ 7 10 RTS IRQ 7 10 RTS I2C 8 SPI 8 SC16IS741IPW 9 VSS SC16IS741IPW 002aaf158 a. I2C-bus interface Fig 3. 13 RX 12 TX 9 VSS 002aaf159 b.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 2. Pin description …continued Symbol Pin Type Description VSS 9 - ground RTS 10 O UART request to send (active LOW). A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin is set to a logic 1.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.1 Trigger levels The SC16IS741 provides independently selectable and programmable trigger levels for both receiver and transmitter interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one character. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR.
PAGE 7
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.2.1 Auto RTS Figure 5 shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.
PAGE 8
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.3 Software flow control Software flow control is enabled through the enhanced feature register and the Modem Control Register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow control options. Table 3.
PAGE 9
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.3.2 TX Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0] or the selectable trigger level in FCR[7:6] Xon1/Xoff2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4] or RX FIFO falls below the lower selectable trigger level in FCR[7:6].
PAGE 10
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.4 Hardware reset, Power-On Reset (POR) and software reset These three reset methods are identical and will reset the internal registers as indicated in Table 4. Table 4 summarizes the state of register. Table 4.
PAGE 11
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.5 Interrupts The SC16IS741 has interrupt generation and prioritization capability. The Interrupt Enable Register (IER) enables each of the interrupts and the IRQ signal in response to an interrupt generation. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions. Table 6.
PAGE 12
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 8 shows Interrupt mode operation. IIR read IIR IRQ HOST IER 1 1 THR 1 1 RHR 002aab042 Fig 8.
PAGE 13
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS741 UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data input line, RX, is idle (see Section 7.7 “Break and time-out conditions”). • The TX FIFO and TX shift register are empty. • There are no interrupts pending except THR.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC MCR[7] = 0 input clock PRESCALER LOGIC (DIVIDE-BY-4) reference clock BAUD RATE GENERATOR LOGIC internal baud rate clock for transmitter and receiver MCR[7] = 1 002aaa233 Fig 10. Prescaler and baud rate generator block diagram DLL and DLH must be written to in order to program the baud rate.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 8. Baud rates using a 3.072 MHz crystal Desired baud rate Divisor used to generate 16× clock Percent error difference between desired and actual 50 2304 0 75 2560 0 110 1745 0.026 134.5 1428 0.034 150 1280 0 300 640 0 600 320 0 1200 160 0 1800 107 0.312 2000 96 0 2400 80 0 3600 53 0.628 4800 40 0 7200 27 1.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8. Register descriptions The programming combinations for register selection are shown in Table 9. Table 9.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SC16IS741 internal registers …continued Register address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.1 Receive Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX pin. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR [1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the XTAL1 clock. 8.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the Line Control Register bit settings. Table 12.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 13. LCR[5] parity selection LCR[5] LCR[4] LCR[3] Parity selection X X 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 forced parity ‘1’ 1 1 1 forced parity ‘0’ Table 14. LCR[2] stop bit length LCR[2] Word length (bits) Stop bit length (bit times) 0 5, 6, 7, 8 1 1 5 11⁄2 1 6, 7, 8 2 Table 15.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.5 Line Status Register (LSR) Table 16 shows the Line Status Register bit settings. Table 16. Line Status Register bits description Bit Symbol Description 7 LSR[7] FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO.
PAGE 23
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 17 shows the Modem Control Register bit settings. Table 17.
PAGE 24
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the modem changes state. Table 18 shows Modem Status Register bit settings. Table 18.
PAGE 25
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of state from LOW to HIGH. The IRQ output signal is activated in response to interrupt generation. Table 19 shows the Interrupt Enable Register bit settings. Table 19.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 20 shows Interrupt Identification Register bit settings. Table 20. Interrupt Identification Register bits description Bit Symbol Description 7:6 IIR[7:6] mirror the contents of FCR[0] 5:1 IIR[5:1] 5-bit encoded interrupt. See Table 21.
PAGE 27
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.10 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows the enhanced feature register bit settings. Table 22. Enhanced Features Register bits description Bit Symbol Description 7 EFR[7] CTS flow control enable logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 23 shows Transmission Control Register bit settings. Table 23.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.15 Receiver FIFO Level register (RXLVL) This register is a read-only register, it reports the fill level of the receive FIFO. That is, the number of characters in the RX FIFO. Table 26. Receiver FIFO Level register bits description Bit Symbol Description 7 - not used; set to zeros 6:0 RXLVL[6:0] number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40) 8.
PAGE 30
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 9. RS-485 features 9.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin.
PAGE 31
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 9.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the XOFF2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard these data.
PAGE 32
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR SDA SCL S P START condition STOP condition mba608 Fig 13. START and STOP conditions The number of data bytes transferred between the START and STOP condition from transmitter to receiver is not limited. Each byte, which must be eight bits long, is transferred serially with the most significant bit first, and is followed by an acknowledge bit (see Figure 14).
PAGE 33
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when a master is a receiver: it must signal an end of data to the transmitter by not signalling an acknowledge on the last byte that has been clocked out of the slave. The acknowledge related clock, generated by the master should still take place, but the SDA line will not be pulled down.
PAGE 34
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Another way for a master to communicate with several different devices would be by using a ‘repeated START’. After the last byte of the transaction was transferred, including its acknowledge (or negative acknowledge), the master issues another START, followed by address byte and data—without effecting a STOP. The master may communicate with a number of different devices, combining ‘reads’ and ‘writes’.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 10.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. Table 28 shows how the SC16IS741’s address can be selected by using A1 and A0 pins.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 29 and Table 30 show the bits’ presentation at the subaddress byte for I2C-bus and SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the UART internal registers. Bit 7 is not used with the I2C-bus interface, but it is used by the SPI interface to indicate a read or a write operation.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 30. Register address byte (SPI) Bit Name Function 7 R/W 1: read from UART 0: write to UART 6:3 A[3:0] UART’s internal register select 2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0 Other values are reserved and should not be used. 0 - not used 12. Limiting values Table 31. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 32. Static characteristics …continued VDD = 2.5 V ± 0.2 V, Tamb = −40 °C to +85 °C; or VDD = 3.3 V ± 0.3 V, Tamb = −40 °C to +95 °C; unless otherwise specified. Symbol Parameter Conditions VDD = 2.5 V Min Max VDD = 3.3 V Min Max Unit Outputs TX, RTS, SO VOH HIGH-level output voltage LOW-level output voltage VOL IOH = −400 μA 1.85 - - - V IOH = −4 mA - - 2.4 - V IOL = 1.6 mA - 0.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 14. Dynamic characteristics Table 33. I2C-bus timing specifications[1] All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V ± 0.2 V, Tamb = −40 °C to +85 °C; or VDD = 3.3 V ± 0.3 V, Tamb = −40 °C to +95 °C; and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF.
PAGE 41
SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR RESET tw(rst) td(rst-SCL) SCL 002aaf472 Fig 21. SCL delay after reset protocol START condition (S) bit 7 MSB (A7) tSU;STA tLOW bit 0 LSB (R/W) bit 6 (A6) tHIGH acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tf tr tSP SDA tSU;DAT tHD;STA tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab489 Rise and fall times refer to VIL and VIH. Fig 22.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR ACK to master SLAVE ADDRESS SDA W A AMSR REGISTER A S SLAVE ADDRESS R A A DATA IRQ td(int_v)modem td(int_clr)modem MODEM pin 002aaf468 Fig 25. Modem input pin interrupt start bit RX next start bit stop bit D0 D1 D2 D3 D4 D5 D6 D7 td(int_v)rx IRQ 002aaf470 Fig 26.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 34. fXTAL dynamic characteristics VDD = 2.5 V ± 0.2 V, Tamb = −40 °C to +85 °C; or VDD = 3.3 V ± 0.3 V, Tamb = −40 °C to +95 °C Symbol Parameter tWH pulse width HIGH tWL pulse width LOW [2] VDD = 2.5 V [1][2] frequency on pin XTAL fXTAL [1] Conditions VDD = 3.3 V Unit Min Max Min Max 10 - 6 - ns 10 - 6 - ns - 48 - 80 MHz Applies to external clock, crystal oscillator max.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR Table 35. SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V ± 0.2 V, Tamb = −40 °C to +85 °C; or VDD = 3.3 V ± 0.3 V, Tamb = −40 °C to +95 °C; and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR CS SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 SO td(int_clr)tx IRQ 002aaf473 R/W = 0; A[3:0] = THR (0x00); CH1 = 0; CH0 = 0 Fig 31. SPI write THR to clear TX INT CS SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 SO D6 D5 D4 D3 D2 D1 D0 td(int_clr)rx IRQ 002aaf474 R/W = 1; A[3:0] = RHR (0x00); CH1 = 0; CH0 = 0 Fig 32.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 34. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 38.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications
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SC16IS741 NXP Semiconductors Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 22. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General features . . . . . . . . . . . . . . . . . . . . . . . .