Datasheet

1. General description
The SC18IS600 is designed to serve as an interface between the standard SPI of a host
(microcontroller, microprocessor, chip set, etc.) and the serial I
2
C-bus. This allows the
host to communicate directly with other I
2
C-bus devices. The SC18IS600 can operate as
an I
2
C-bus master-transmitter or master-receiver. The SC18IS600 controls all the I
2
C-bus
specific sequences, protocol, arbitration and timing.
2. Features and benefits
 SPI slave interface
 SPI Mode 3
 Single master I
2
C-bus controller
 Four General Purpose Input/Output (GPIO) pins
 Two quasi-bidirectional I/O pins
 5 V tolerant I/O pins
 High-speed SPI: Up to 1.2 Mbit/s
 High-speed I
2
C-bus: 400 kbit/s
 96-byte transmit buffer
 96-byte receive buffer
 2.4 V to 3.6 V operation
 Power-down mode with WAKEUP
pin
 Internal oscillator
 Active LOW interrupt output
 Available in very small TSSOP16 and HVQFN24 packages
3. Ordering information
SC18IS600
SPI to I
2
C-bus interface
Rev. 6 — 4 May 2012 Product data sheet
Table 1. Ordering information
Type number Package
Name Description Version
SC18IS600IPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
SC18IS600IBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals;
body 4 × 4 × 0.85 mm
SOT616-3