SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter (DUART) Rev. 07 — 19 December 2007 Product data sheet 1. General description The SC28L92 is a pin and function replacement for the SCC2692 and SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on power-up is that of the SC26C92.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 2. Features n Member of IMPACT family: 3.3 V to 5.0 V, −40 °C to +85 °C and 68xxx or 80xxx bus interface for all devices n Dual full-duplex independent asynchronous receiver/transmitters n 16 character FIFOs for each receiver and transmitter n Pin programming selects 68xxx or 80xxx bus interface n Programmable data format u 5 data to 8 data bits plus parity u Odd, even, no parity or force parity u 1 stop, 1.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter n n n n n On-chip crystal oscillator Power-down mode Receiver time-out mode Single 3.3 V or 5 V power supply Powers up to emulate SC26C92 3. Ordering information Table 1. Ordering information VCC = 3.3 V ± 10 % or VCC = 5.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 4.
SC28L92 NXP Semiconductors 3.3 V/5.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 5. Pinning information n.c. 1 40 IP2 A0 2 41 IP6 IP3 3 42 IP5 A1 4 43 IP4 IP1 5 44 VCC A2 6 5.1 Pinning A3 7 39 CEN IP0 8 38 RESET WRN 9 37 X2 RDN 10 36 X1/CLK RxDB 11 35 RxDA SC28L92A1A I/M 12 34 n.c. (80xxx mode) TxDB 13 33 TxDA D4 26 D2 27 D0 28 42 IP5 41 IACKN 40 IP2 D6 25 INTRN 24 n.c.
SC28L92 NXP Semiconductors 34 IP2 35 IP6 36 IP5 37 IP4 38 VCC 39 VCC 40 A0 41 IP3 42 A1 43 IP1 44 A2 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter A3 1 33 CEN IP0 2 32 RESET WRN 3 31 X2 RDN 4 30 X1/CLK RxDB 5 29 RxDA TxDB 6 SC28L92A1B 28 TxDA OP1 7 (80xxx mode) 27 OP0 OP3 8 26 OP2 OP5 9 25 OP4 OP7 10 24 OP6 I/M 11 D6 19 D4 20 D2 21 D0 22 37 IP4 36 IP5 35 IACKN 34 IP2 INTRN 18 GND 17 GND 16 D7 15 D5 14 D3 13 D1 12 23 n.c.
SC28L92 NXP Semiconductors 37 n.c. 38 IP2 39 IP6 40 IP5 41 IP4 42 VCC 43 n.c. 44 A0 45 IP3 46 A1 48 A2 terminal 1 index area 47 IP1 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter A3 1 36 n.c. IP0 2 35 CEN WRN 3 34 RESET RDN 4 33 X2 RxDB 5 32 X1/CLK n.c. 6 I/M 7 TxDB 8 29 OP0 OP1 9 28 OP2 OP3 10 27 OP4 OP5 11 26 OP6 OP7 12 25 n.c. 31 RxDA SC28L92A1BS 30 TxDA D2 22 D0 23 n.c. 24 39 IACKN 38 IP2 37 n.c.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 5.2 Pin description Table 2. Symbol Pin description for 80xxx bus interface (Intel) Pin Type Description PLCC44 QFP44 HVQFN48 I/M 12 11 7 I Bus configuration: When HIGH or not connected configures the bus interface to the conditions shown in this table.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 2. Symbol Pin description for 80xxx bus interface (Intel) …continued Pin Type Description PLCC44 QFP44 HVQFN48 TxDA 33 28 30 O Channel A transmitter serial data output: The least significant bit is transmitted first. This output is held in the Mark condition when the transmitter is disabled, Idle or when operating in local loopback mode. See note on drive levels at block diagram (Figure 1).
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 2. Symbol Pin description for 80xxx bus interface (Intel) …continued Pin Type Description Pwr Ground PLCC44 QFP44 HVQFN48 GND 22 n.c. 1, 23, 34 23 [1] 16, 17 18[1] 6, 13, 24, 25, Pwr 36, 37, 43 Not connected HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 3. Symbol Pin description for 68xxx bus interface (Motorola) …continued Pin Type Description 19 O Interrupt request: Active LOW, open-drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. This pin requires a pull-up. 30 32 I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 3. Symbol Pin description for 68xxx bus interface (Motorola) …continued Pin Type Description 45 I Input 3: General purpose input or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. 37 41 I Input 4: General purpose input or channel A receiver external clock input (RxCA).
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their output buffers are changed to the open-drain active LOW configuration. The OP pins may be used for DMA and modem control as well (see Section 7.4). 6.1.4 FIFO configuration Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be configured to operate at a fill capacity of either 8 bytes or 16 bytes.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 6.2.2 Baud rate generator The baud rate generator operates from the oscillator or external clock input at the X1 input and is capable of generating 28 commonly used data communications baud rates ranging from 50 kBd to 38.4 kBd. Programming bit 0 of MR0 to a logic 1 gives additional baud rates of 57.6 kBd, 115.2 kBd and 230.4 kBd (500 kHz with X1 at 8.0 MHz).
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter counter/timer input clock n = -------------------------------------------------------------------------2 × 16 × ( desired baud rate ) (1) Often this division will result in a non-integer number; 26.3 for example. One may only program integer numbers to a digital divider. Therefore 26 (0x1A) would be chosen. If 26.7 were the result of the division, then 27 (0x1B) would be chosen. This gives a baud rate error of 0.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Counter/Timer upper register. These commands have slight differences depending on the mode of operation. Please see the detail of the commands in Section 7.3.3 “Command registers”. 6.2.7 Time-out mode caution When operating in the special time-out mode, it is possible to generate what appears to be a false interrupt, i.e., an interrupt without a cause.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 6.2.10 Output port The output ports are controlled from six places: the OPCR, OPR, MR, Command, SOPR and ROPR registers. The OPCR register controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1 must be LOW in order for the character to be transmitted. The transmitter will check the state of the CTS input at the beginning of each character transmitted. If it is found to be HIGH, the transmitter will delay the transmission of any following characters until the CTS has returned to the LOW state.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 6.3.4 Receiver FIFO The Rx FIFO consists of a First-In-First-Out (FIFO) stack with a capacity of 8 or 16 characters. Data is loaded from the receive shift register into the topmost empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all 8 or 16 stack positions are filled with data.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter A receiver reset will discard the present shift register date, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of the FIFO and realign the FIFO read/write pointers. 6.3.7 Watchdog A watchdog timer is associated with each receiver. Its interrupt is enabled by MR0[7]. The purpose of this timer is to alert the control processor that characters are in the Rx FIFO which have not been read.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 6.3.9 Time-out mode caution When operating in the special time-out mode, it is possible to generate what appears to be a false interrupt, i.e., an interrupt without a cause. This may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i.e., the data stream has started again. (The interrupt latency is longer than the pause in the data stream.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 5. Registers for channels A and B …continued Register name Channel A register Channel B register Access Command Register CRA CRB W only Receiver FIFO RxFIFOA RxFIFOB R only Transmitter FIFO TxFIFOA TxFIFOB W only Mnemonic Access Table 6.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 11. CR - Command Register 7 6 5 4 channel command code Table 12. 3 2 1 0 disable Tx enable Tx disable Rx enable Rx SR - channel Status Register 7 6 5 4 3 2 1 0 received break framing error parity error overrun error TxEMT TxRDY RxFULL RxRDY 3 2 1 0 RxRDYA TxRDYA 1 0 RxRDYA FFULLA TxRDYA 2 1 0 2 1 0 Table 13.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 21. ROPR - Reset Output Port bits Register (ROPR) 7 6 5 4 3 2 1 0 reset OP7 reset OP6 reset OP5 reset OP4 reset OP3 reset OP2 reset OP1 reset OP0 Table 22.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 24. MR0A - Mode Register 0 channel A (address 0x0) bit description …continued Bit Symbol Description 3 FIFOSIZE FIFO size for channel A and channel B. Selects the FIFO depth at 8-byte or 16-byte. 0 = 8 bytes 1 = 16 bytes 2 BAUDRATE EXTENDED I Bits MR0[2:0] are used to select one of the six baud rate groups. See Table 35 for the group organization.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.1.2 Mode Register 1 channel A (MR1A) Table 27. MR1A - Mode Register 1 channel A (address 0x0) bit allocation MR1A is accessed when the channel A MR pointer points to MR1. The pointer is set to MR1 by RESET or by a set pointer command applied via CR command 1. After reading or writing MR1A, the pointer will point to MR2A[1].
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 28. MR1A - Mode Register 1 channel A (address 0x0) bit description …continued Bit Symbol Description 2 PARITYTYPE Channel A parity type select 0 = even 1 = odd This bit selects the parity type (odd or even) if the with parity mode is programmed by MR1A[4:3], and the polarity of the forced parity bit if the force parity mode is programmed. It has no effect if the no parity mode is programmed.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 30. MR2A - Mode Register 2 channel A (address 0x0) bit description …continued Bit Symbol Description 5 - Channel A transmitter Request To Send (RTS) control. 0 = No RTS control 1 = RTS control This bit controls the deactivation of the RTSAN output (OP0) by the transmitter. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0].
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 31. DUART mode description Mode Description Normal The transmitter and receiver operating independently. Automatic echo Places the channel in the automatic echo mode, which automatically retransmits the received data. The following conditions are true while in automatic echo mode: 1. Received data is reclocked and retransmitted on the TxDA output 2. The receive clock is used for the transmitter 3.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 32. MR2A[3:0] (hexadecimal) Stop bit length[1] B 1.750 C 1.813 D 1.875 E 1.938 F 2.000 [1] 7.3.1.4 Stop bit length …continued Add 0.5 to values shown for 0 to 7 if channel is programmed for 5 bit per character Mode Register 0 channel B (MR0B) MR0B (address 0x8) is accessed when the channel B MR pointer points to MR1. The pointer is set to MR0 by RESET or by a set pointer command applied via CRB.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.2 Clock select registers Table 33. CSRA - Clock select register channel A (address 0x1) and CSRB - Clock select register channel B (address 0x9) bit allocation 7 6 5 4 3 receiver clock select code 7.3.2.1 2 1 0 transmitter clock select code Clock Select Register channel A (CSRA) Table 34.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 36. Bit rate generator characteristics[1] Crystal or clock = 3.6864 MHz. Normal rate (baud) Actual 16× clock (kHz) Error (%) 50 0.8 0 75 1.2 0 110 1.759 −0.069 134.5 2.153 0.059 150 2.4 0 200 3.2 0 300 4.8 0 600 9.6 0 1050 16.756 −0.260 1200 19.2 0 1800 28.8 0 2000 32.056 0.175 2400 38.4 0 4800 76.8 0 7200 115.2 0 9600 153.6 0 19200 307.2 0 38400 614.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.3 Command registers Table 38. 7 CRA - Command register channel A (address 0x2) and CRB - Command register channel B (address 0xA) bit allocation 6 5 4 channel command code 7.3.3.1 3 2 1 0 disable Tx enable Tx disable Rx enable Rx Command Register channel A (CRA) CRA is a register used to supply commands to channel A.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 40. 7.3.3.2 Miscellaneous commands …continued Command Description 0110 Start break. Forces the TxDA output LOW (spacing). If the transmitter is empty the start of the break condition will be delayed up to two bit times. If the transmitter is active the break begins when transmission of the character is completed.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.4 Status registers 7.3.4.1 Status Register channel A (SRA) Table 41. SRA - Status register channel A (address 0x1) bit allocation 7 6 5 4 3 2 1 0 received break[1] framing error[1] parity error[1] overrun error TxEMTA TxRDYA RxFULLA RxRDYA [1] These status bits are appended to the corresponding data character in the receive FIFO.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 42. SRA - Status register channel A (address 0x1) bit description …continued Bit Symbol Description 4 - Channel A overrun error. 0 = no 1 = yes This bit, when set, indicates that one or more characters in the received data stream have been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.4.2 Status Register channel B (SRB) Table 43. SRB - Status register channel B (address 0x9) bit allocation 7 6 5 4 3 2 1 0 received break[1] framing error[1] parity error[1] overrun error TxEMTB TxRDYB RxFULLB RxRDYB [1] These status bits are appended to the corresponding data character in the receive FIFO.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 45. OPCR - Output configuration control register (address 0xD) bit description Bit Symbol Description 3 and 2 - OP3 output select 00 = The complement of OPR[3] 01 = The counter/timer output, in which case OP3 acts as an open-drain output. In the timer mode, this output is a square wave at the programmed frequency.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.6 Set Output Port bits Register (SOPR) Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows software to set individual bits without keeping a copy of the OPR bit configuration. Table 46.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.7 Reset Output Port bits Register (ROPR) Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This allows software to reset individual bits without keeping a copy of the OPR bit configuration. Table 48.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.8 Output Port Register (OPR) Table 50. OPR - Output port register (no address) bit allocation The output pins (OP pins) drive the complement of the data in this register as controlled by SOPR and ROPR. 7 6 5 4 3 2 1 0 OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Table 51.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.9 Auxiliary Control Register (ACR) Table 52. ACR - Auxiliary control register (address 0x4) bit allocation 7 BRG set select 6 5 4 counter/timer mode and clock source select Table 53.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.10 Input Port Change Register (IPCR) Table 55. IPCR - Input port change register (address 0x4) bit allocation 7 6 5 4 3 2 1 0 delta IP3 delta IP2 delta IP1 delta IP0 state of IP3 state of IP2 state of IP1 state of IP0 Table 56. IPCR - Input port change register (address 0x4) bit description Bit Symbol Description 7 to 4 - IP3, IP2, IP1 and IP0 change of state.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 58. ISR - Interrupt status register (address 0x5) bit description …continued Bit Symbol Description 6 - Channel B change in break. 0 = not active 1 = active This bit, when set, indicates that the channel B receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a channel B reset break change interrupt command. 5 RxRDYB RxB interrupt.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.12 Interrupt Mask Register (IMR) The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1 the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 7.3.13 Interrupt Vector Register (IVR; 68xxx mode) or General Purpose register (GP; 80xxx mode) This register stores the Interrupt Vector. It is initialized to 0x0F on hardware reset and is usually changed from this value during initialization of the SC28L92. The contents of this register will be placed on the data bus when IACKN is asserted LOW or a read of address 0xC is performed.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter The counter ready status bit (ISR[3]) is set once each cycle of the square wave. The bit is reset by a stop counter command (read with A3 to A0 = 1111). The command however, does not stop the C/T. The generated square wave is output on OP3 if it is programmed to be the C/T output. In the counter mode, the value C/T loaded into CTPU and CTPL by the CPU is counted down to 0.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter MR2[4] is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input is driven HIGH, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of the receiver that will be connected to the transmitter’s CTS input.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 9. Static characteristics Table 65. Static characteristics, 5 V operation[1] VCC = 5 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter VIL input LOW voltage VIH input HIGH voltage output LOW voltage VOL Conditions Min Typ Max Unit - - 0.8 V except pin X1/CLK 2.4 1.5 - V pin X1/CLK 0.8VCC 2.4 - V - 0.2 0.4 V VCC − 0.5 - - V IOL = 2.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 001aae302 60 tDD (ns) (1) 40 (2) 20 12 pF 30 pF 100 pF 125 pF 230 pF 0 0 40 80 120 160 200 240 CL (pF) (1) VCC = 3.3 V; Tamb = 25 °C (2) VCC = 5.0 V; Tamb = 25 °C Bus cycle times: 80xxx mode: tDD + tRWD = 70 ns for VCC = 5 V or 40 ns for VCC = 3.3 V + rise and fall time of control signals.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 66. Static characteristics, 3.3 V operation[1] VCC = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min VIL input LOW voltage - 0.65 0.2VCC V VIH input HIGH voltage 0.8VCC 1.7 - V VOL output LOW voltage - 0.2 0.4 V IOL = 2.4 mA Typ Max Unit VCC − 0.5 VCC − 0.2 - V VI = 0 V to VCC −0.5 +0.05 +0.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 10. Dynamic characteristics Table 67. Dynamic characteristics, 5 V operation[1] VCC = 5.0 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise specified.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 67. Dynamic characteristics, 5 V operation[1] …continued VCC = 5.0 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise specified.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter [7] Minimum DACKN time is ((tDCR or tDCW) tCSC + 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Table 68. Dynamic characteristics, 3.3 V operation[1] …continued VCC = 3.3 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise specified.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter [7] Minimum DACKN time is ((tDCR or tDCW) tCSC + 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter tCSC X1/CLK tAS A0 to A3 tCS tCH R/WN tAH tRWD CEN tDD D0 to D7 tDF not valid data valid tDAH tDA DACKN tDCR tDAT 001aae306 DACKN LOW requires two rising edges of X1 clock after CEN is LOW. Fig 12. Bus timing, read cycle (68xxx mode) tCSC X1/CLK tAS A0 to A3 tCS tCH R/WN tAH tRWD CEN tDH tDS D0 to D7 tDAH DACKN tDCW tDAT 001aae308 DACKN LOW requires two rising edges of X1 clock after CEN is LOW.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter tCSC X1/CLK INTRN IACKN tDD tDF D0 to D7 tDCR tDAH DACKN tDAL tCSD tDAT 001aae309 DACKN LOW requires two rising edges of X1 clock after CEN is LOW. Fig 14. Interrupt cycle timing (68xxx mode) RDN tPS tPH IP0 to IP6 001aae311 a. Input pins. WRN tPD OP0 to OP6 old data new data 001aae312 b. Output pins. Fig 15. Port timing SC28L92_7 Product data sheet © NXP B.V. 2007. All rights reserved. Rev.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter VM WRN tIR interrupt output(1) VOL + 0.5 V VOL RDN VM tIR interrupt output(1) VOL + 0.5 V VOL 001aae313 The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.2 V above VOL. This point represents noise margin that assures true switching has occurred.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter X1/CLK C/T clock RxC TxC tCLK tCTC tRX tTX VCC resistor required for TTL input CLK X1 tCLK tCTC tRX tTX 3 pF parasitic capacitance 470 Ω X2 (must be left open) SC28L92 X1 2 pF C1 50 kΩ to 100 kΩ 3.6864 MHz C2 4 pF X2 to UART circuit 3 pF parasitic capacitance 001aae314 C1 = C2 ∼ 24 pF for CL = 13.5 pF. For the oscillator feedback loop, the capacitors C1 and C2 are in series.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter D1 TxD D2 D3 break D4 D6 transmitter enabled TxRDY (SR2) WRN D1 D8 D9 CTSN(1) start break stop break D10 (IP0) D11 will not be written to the TxFIFO D12 RTSN(2) (OP0) OPR(0) = 1 OPR(0) = 1 001aae317 (1) Timing shown for MR2[4] = 1. (2) Timing shown for MR2[5] = 1. Fig 20.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter master station: bit 9 TxD ADD#1 1 bit 9 bit 9 D0 ADD#2 1 0 transmitter enabled TxRDY (SR) WRN ADD#2 MR1[4:3] = 11 ADD#1 D0 MR1[2] = 0 MR1[2] = 1 peripheral station: bit 9 RxD 0 MR1[2] = 1 bit 9 ADD#1 1 bit 9 bit 9 D0 bit 9 ADD#2 1 0 0 receiver enabled RxRDY (SR) RDN/WRN MR1[4:3] = 11 ADD#1 status data status data D0 ADD#2 001aae319 Fig 22. Wake-up mode timing 12. Test information I = 2.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 13. Package outline PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 β 18 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE k 16.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.1 0.25 0.05 1.85 1.65 0.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm D SOT778-4 A B terminal 1 index area E A A1 c detail X C e1 e v w b 1/2 e 13 M M y1 C C A B C y 24 L 25 12 e e2 Eh 1/2 e 1 36 terminal 1 index area 48 37 X Dh 0 2.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 14.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 71.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 16. Revision history Table 72. Revision history Document ID Release date Data sheet status Change notice Supersedes SC28L92_7 20071219 Product data sheet - SC28L92_6 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
SC28L92 NXP Semiconductors 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 19. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 7 7.1 7.2 7.3 7.3.1 7.3.1.1 7.3.1.2 7.3.1.3 7.3.1.4 7.3.1.5 7.3.1.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .