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Table Of Contents

1. General description

Meets JEDEC Specification 42.4 TSE2002B1, 3 Jun 2009. The NXP Semiconductors

SE97B measures temperature from −40 °C to +125 °C with JEDEC Grade B ±1 °C

maximum accuracy between +75 °C and +95 °C critical zone and also provide 256 bytes

of EEPROM memory communicating via the I

C-bus/SMBus. It is typically mounted on a

DDR3 Dual In-Line Memory Module (DIMM) measuring the DRAM temperature in

accordance with the new JEDEC (JC-42.4) Mobile Platform Memory Module Temperature

Sensor Component specification and also replacing the Serial Presence Detect (SPD)

which is used to store memory module and vendor information.

The SE97B thermal sensor and EEPROM operates over the V

range of 3.0 V to 3.6 V.

The TS consists of a ΔΣ Analog to Digital Converter (ADC) that monitors and updates its

own temperature readings 10 times per second, converts the reading to a digital data, and

latches them into the data temperature register. User-programmable registers, the

specification of upper/lower alarm and critical temperature trip points, EVENT

output

control, and temperature shutdown, provide flexibility for DIMM temperature-sensing

applications.

When the temperature changes beyond the specified boundary limits, the SE97B outputs

an EVENT

signal using an open-drain output that can be pulled up between 0.9 V and

3.6 V. The user has the option of setting the EVENT

output signal polarity as either an

active LOW or active HIGH comparator output for thermostat operation, or as a

temperature event interrupt output for microprocessor-based systems. The EVENT

output

can also be configured as only a critical temperature output.

The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes

(address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write

Protected (RWP) by software. This allows DRAM vendor and product information to be

stored and write protected. The upper 128 bytes (address 80h to FFh) are not write

protected and can be used for general purpose data storage.

The SE97B has a single die for both the temp sensor and EEPROM for higher reliability

and supports the industry-standard 2-wire I

C-bus/SMBus serial interface. The SMBus

TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID

registers provide the ability to confirm the identity of the device. Three address pins allow

up to eight devices to be controlled on a single bus.

The SE98B is available as the SE97B thermal sensor only.

SE97B

DDR memory module temp sensor with integrated SPD

Rev. 01 — 27 January 2010 Product data sheet

Summary of content (53 pages)

PAGE 1
SE97B DDR memory module temp sensor with integrated SPD Rev. 01 — 27 January 2010 Product data sheet 1. General description Meets JEDEC Specification 42.4 TSE2002B1, 3 Jun 2009. The NXP Semiconductors SE97B measures temperature from −40 °C to +125 °C with JEDEC Grade B ±1 °C maximum accuracy between +75 °C and +95 °C critical zone and also provide 256 bytes of EEPROM memory communicating via the I2C-bus/SMBus.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 1. Comparison of SE97 versus SE97B features Feature JEDEC specification Bit 8 ‘1’ Thermal Sensor shutdown Bit 8 ‘0’ Thermal Sensor active SE97 SE97B old JEDEC specification new JEDEC specification no SMBus Timeout I2C-bus maximum frequency I2C SMBus Timeout 25 ms to 35 ms SMBus Timeout 25 ms to 35 ms 400 kHz VIL(max) = 0.3 × VDD; VIH(min) = 0.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Programmable hysteresis threshold: off, 0 °C, 1.5 °C, 3 °C, 6 °C Over/under/critical temperature EVENT output B-grade accuracy: ±0.5 °C/±1 °C (typ./max.) → +75 °C to +95 °C ±1.0 °C/±2 °C (typ./max.) → +40 °C to +125 °C ±2.0 °C/±3 °C (typ./max.) → −40 °C to +125 °C 2.3 Serial EEPROM features Read and write voltage range: 3.0 V to 3.6 V Operating current: Write → 0.6 mA (typ.) for 3.5 ms (typ.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 5.
PAGE 5
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 6. Pinning information 6.1 Pinning terminal 1 index area A0 1 A1 2 8 VDD 7 EVENT SE97BTP A2 3 6 SCL VSS 4 5 SDA 002aae311 Transparent top view Fig 2. Pin configuration for HWSON8 6.2 Pin description Table 3. Pin description Symbol Pin Type Description A0 1 I I2C-bus/SMBus slave address bit 0 with internal pull-down. This input is overvoltage tolerant to support software write protection.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7. Functional description 7.1 Serial bus interface The SE97B communicates with a host controller by means of the 2-wire serial bus (I2C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The device supports SMBus, I2C-bus Standard-mode and Fast-mode.
PAGE 7
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.3 EVENT output condition The EVENT output indicates conditions such as the temperature crossing a predefined boundary. The EVENT modes are very configurable and selected using the configuration register (CONFIG). The interrupt mode or comparator mode is selected using CONFIG[0], using either TCRIT/UPPER/LOWER or TCRIT only temperature bands (CONFIG[2]) as modified by hysteresis (CONFIG[10:9]).
PAGE 8
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Tth(crit) − Thys temperature (°C) critical Ttrip(u) − Thys Ttrip(u) − Thys Upper Boundary Alarm Tamb Ttrip(l) − Thys Lower Boundary Alarm Ttrip(l) − Thys time EVENT in Comparator mode EVENT in Interrupt mode software interrupt clear EVENT in ‘Critical Temp only’ mode (1) (2) (1) (3) (4) (3)(5) (7) (6) (4) (2) 002aae763 Refer to Table 4 for figure note information. Fig 4. Table 4.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.3.2 EVENT thresholds 7.3.2.1 Alarm window The device provides a comparison window with an UPPER trip point and a LOWER trip point, programmed through the Upper Boundary Alarm Trip register (02h), and Lower Boundary Alarm Trip register (03h).
PAGE 10
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.3.3 EVENT operation modes 7.3.3.1 Comparator mode In comparator mode, the EVENT output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the Upper Boundary Alarm Trip register or below the value programmed in the Lower Boundary Alarm Trip register or above the Critical Alarm Trip register if Tth(crit) only is selected).
PAGE 11
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.4 Conversion rate The conversion time is the amount of time required for the ADC to complete a temperature measurement for the local temperature sensor. The conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one second—the faster the conversion rate, the faster the temperature reading is updated.
PAGE 12
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 5 shows the default values and the example value to be programmed to these registers. Table 5. Registers to be initialized Register Default value Example value Description 01h 0000h 0209h Configuration register • • • hysteresis = 1.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD read START bit S 0 0 host detects SMBus ALERT Fig 5. acknowledge no acknowledge Alert Response Address 0 1 1 0 STOP bit device address 0 1 0 0 master sends a START bit, ARA and a read command 0 1 1 A2 A1 A0 Slave acknowledges and sends its slave address. The last bit of slave address is hard coded '0'.
PAGE 14
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 (cont.) SCL A6 SDA A5 A4 A3 A2 A1 D7 A0 S W device address and write START by host 1 2 3 4 5 6 7 D15 D14 D13 D12 D11 D10 D9 D6 D5 D4 D3 D2 D1 (cont.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 1 2 3 4 5 6 7 8 9 (cont.) SCL A6 SDA A5 A4 A3 A2 A1 (cont.) A0 S R START by host device address and read A ACK by device 1 2 3 4 5 6 7 8 D15 D14 D13 D12 D11 D10 D9 D8 9 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 SCL SDA A A returned most significant byte data ACK by host returned least significant byte data P NACK STOP by host 002aac687 A = ACK = Acknowledge bit.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.10.1 Write operations 7.10.1.1 Byte Write In Byte Write mode the master creates a START condition and then broadcasts the slave address, byte address, and data to be written. The slave acknowledges all 3 bytes by pulling down the SDA line during the ninth clock cycle following each byte. The master creates a STOP condition after the last ACK from the slave, which then starts the internal write operation (see Figure 11).
PAGE 17
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.10.1.3 Acknowledge polling Acknowledge polling can be used to determine if the SE97B is busy writing or is ready to accept commands. Polling is implemented by sending a ‘Selective Read’ command (described in Section 7.10.3 “Read operations”) to the device. The SE97B will not acknowledge the slave address as long as internal write is in progress. 7.10.
PAGE 18
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Up to eight memory devices can be connected on a single I2C-bus. Each one is given a 3-bit on the hardware selectable address (A2, A1, A0) inputs. The device only responds when the 4-bit fixed and hardware selectable bits are matched. The 8th bit is the read/write bit. This bit is set to 1 or 0 for read and write protection, respectively.
PAGE 19
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.10.2.2 Reversible Write Protection (RWP) and Clear Reversible Write Protection (CRWP) If the software write-protection has been set with the RWP instruction, it can be cleared again with a CRWP instruction. The two instructions, RWP and CRWP have the same format as a Byte Write instruction, but with a different setting for the hardware address pins (as shown in Table 6).
PAGE 20
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.10.3 Read operations 7.10.3.1 Current address read In Standby mode, the SE97B internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If the ‘previous’ byte was the last byte in memory, then the address counter will point to the first memory byte, and so on.
PAGE 21
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 7.10.3.3 Sequential read If the master acknowledges the first data byte transmitted by the SE97B, then the device will continue transmitting as long as each data byte is acknowledged by the master (Figure 17). If the end of memory is reached during sequential Read, the address counter will ‘wrap around’ to the beginning of memory, and so on.
PAGE 22
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8. Register descriptions 8.1 Register overview This section describes all the registers used in the SE97B. The registers are used for latching the temperature reading, storing the low and high temperature limits, configuring, the hysteresis threshold of the ADC, as well as reporting status. The device uses the pointer register to access these registers.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.2 CAP — Capability register (00h, 16-bit read-only) Table 10. CAP - Capability register (address 00h) bit allocation Bit 15 14 13 12 Symbol 11 10 9 8 RFU Default 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol EVSD TMOUT VHV TRES TRES WRNG HACC BCAP Default 1 1 1 1 0 1 1 1 Access R R R R R R R R Table 11.
PAGE 24
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.3 CONFIG — Configuration register (01h, 16-bit read/write) Table 12. CONFIG - Configuration register (address 01h) bit allocation Bit 15 14 13 Symbol 12 11 10 RFU 9 HEN 8 SHMD Default 0 0 0 0 0 0 0 0 Access R R R R R R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol CTLB AWLB CEVNT ESTAT EOCTL CVO EP EMD Default 0 0 0 0 0 0 0 0 Access R/W R/W W R R/W R/W R/W R/W Table 13.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 13. Configuration register (address 01h) bit description …continued Bit Symbol Description 8 SHMD Shutdown Mode. 0 — Temperature Sensor is active and converting (default). 1 — disabled Temperature Sensor will not generate interrupts or update the temperature data. When shut down, the thermal sensor diode and ADC are disabled to save power, no events will be generated.
PAGE 26
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 13. Configuration register (address 01h) bit description …continued Bit Symbol Description 3 EOCTL EVENT Output Control. 0 — EVENT output disabled (default) 1 — EVENT output enabled When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked. 2 CVO Critical Event Only.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 14.
PAGE 28
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.4 Temperature format The temperature data from the temperature read back register is an 11-bit 2’s complement word with the least significant bit (LSB) equal to 0.125 °C (resolution). • A value of 019Ch will represent 25.75 °C • A value of 07C0h will represent 124 °C • A value of 1E64h will represent −25.75 °C. The unused LSB (bit 0) is set to ‘0’. Bit 11 will have a resolution of 128 °C.
PAGE 29
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.5 Temperature Trip Point registers While writing to the 16-bit Upper, Lower, or Critical Boundary Alarm Trip registers, please ensure that both bytes get written before doing a new START or STOP to ensure that a valid temperature value gets written into the registers. 8.5.1 UPPER — Upper Boundary Alarm Trip register (02h, 16-bit read/write) The value is the upper threshold temperature value for Alarm mode.
PAGE 30
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.5.2 LOWER — Lower Boundary Alarm Trip register (03h, 16-bit read/write) The value is the lower threshold temperature value for Alarm mode. The data format is 2’s complement with bit 2 = 0.25 °C. RFU bits will always report zero. Interrupts will respond to the presently programmed boundary values.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.6 TEMP — Temperature register (05h, 16-bit read-only) Table 22. TEMP - Temperature register bit allocation Bit 15 14 13 12 11 10 9 8 Symbol ACT AAW BAW SIGN 128 °C 64 °C 32 °C 16 °C Default 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol 8 °C 4 °C 2 °C 1 °C 0.5 °C 0.25 °C 0.
PAGE 32
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.7 MANID — Manufacturer’s ID register (06h, 16-bit read-only) The SE97B Manufacturer’s ID register is intended to match NXP Semiconductors PCI SIG (1131h). Table 24.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 8.9 SMBUS — SMBus register (22h, 8-bit read/write) Table 26.
PAGE 34
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 27. SMBus Time-out register bit description …continued Bit Symbol Description 1 RFU reserved; always ‘0’ 0 DisableARA Disable SMBus Alert Response Address (ARA). 0 — SMBus ARA is enabled 1 — disable SMBus ARA (default) When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be altered until unlocked. Table 28.
PAGE 35
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 9. Application design-in information In a typical application, the SE97B behaves as a slave device and interfaces to a bus master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host, and asserts when the temperature reading exceeds the programmed values in the alarm registers. The A0, A1 and A2 pins are directly connected to VDD or VSS without any pull-up resistors.
PAGE 36
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 9.1 SE97B in memory module application Figure 21 shows the SE97B being placed in the memory module application. The SE97B is centered in the memory module to monitor the temperature of the DRAM and also to provide a 2-kbit EEPROM as the Serial Presence Detect (SPD). In the event of overheating, the SE97B triggers the EVENT output and the memory controller throttles the memory bus to slow the DRAM.
PAGE 37
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD VOL(SDA) = LOW-level output voltage on pin SDA VOL(EVENT) = LOW-level output voltage on pin EVENT IOL(sink)(SDA) = SDA output current LOW IOL(sink)EVENT = EVENT output current LOW Calculation example: Tamb (typical temperature inside the notebook) = 50 °C IDD(AV) = 400 μA VDD = 3.6 V Maximum VOL(SDA) = 0.4 V IOL(sink)(SDA) = 1 mA VOL(EVENT) = 0.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 10. Limiting values Table 29. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD supply voltage −0.5 +4.3 V Vn voltage on any other pin SDA, SCL, A1, A2, EVENT pins −0.5 +4.3 V VA0 voltage on pin A0 overvoltage input; A0 pin −0.5 +12.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 31. DC characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design. Symbol Parameter Conditions VDD supply voltage IDD(AV) average supply current SMBus inactive IDD supply current Isd(VDD) Min Typ Max Unit 3.0 - 3.6 V - 210 320 μA fSCL = 400 kHz - 250 400 μA supply voltage shutdown mode current SMBus inactive - 0.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 002aaf180 320 IDD(AV) (μA) IDD(AV) (μA) VDD = 3.6 V 3.0 V 220 002aaf181 350 VDD = 3.6 V 3.0 V 250 120 150 20 −40 0 40 80 120 Tamb (°C) 50 −40 I2C-bus inactive. 0 40 80 120 Tamb (°C) fSCL = 400 kHz. Fig 22. Average supply current Fig 23. Average supply current 002aaf182 5 Isd(VDD) (μA) 002aaf183 0.20 VOL (V) 0.16 3 VDD = 3.6 V 3.0 V 0.12 0.08 1 VDD = 3.6 V 3.0 V 0.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 002aaf186 0.20 VOL (V) 0.16 0.12 0.12 VDD = 3.6 V 3.0 V 0.08 0.04 0 40 80 120 Tamb (°C) Fig 28. EVENT output VOL at IOL = 0.7 mA 0.12 0 −40 80 120 Tamb (°C) 002aad886 15 conversion rate (conv/s) 13 0.08 9 0.04 7 40 40 11 VDD = 3.6 V 3.0 V 0 0 Fig 29. EVENT output VOL at IOL = 2.1 mA 002aaf188 0.20 VOL (V) 0.16 0 −40 VDD = 3.6 V 3.0 V 0.08 0.04 0 −40 002aaf187 0.20 VOL (V) 0.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 002aad889 3.0 Vth (V) 2.5 1.5 2.0 1.0 1.5 0.5 1.0 −40 0 40 80 120 Tamb (°C) 002aad890 2.0 Vth (V) 0 −40 For temp sensor conversion. 0 40 80 120 Tamb (°C) For EEPROM read operation. Fig 34. Average power-on threshold voltage 002aae107 3.0 Vth (V) Fig 35. Average power-on threshold voltage 002aad892 5 temp error (˚C) 2.5 3 2.0 1 1.5 1.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 002aaf189 3.0 Tlim(acc) (°C) 002aaf178 120 thermal response (%) 1.5 80 0 40 −1.5 −3.0 −40 0 40 80 120 Tamb (°C) 0 0 1 2 3 4 5 time (s) From 25 °C (air) to 120 °C (oil bath) at 3.3 V. Fig 38. SE97B temperature accuracy Fig 39. Package thermal response SE97B_1 Product data sheet © NXP B.V. 2010. All rights reserved. Rev.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 32. SMBus AC characteristics VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design. The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I2C-bus from DC to 400 kHz.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD [9] The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal write cycle. During the internal write cycle, SDA is released by the slave and the device does not acknowledge external commands.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 12. Package outline HWSON8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm SOT1069-2 X A B D A2 A E A1 A3 terminal 1 index area detail X e1 terminal 1 index area e 1 4 C C A B C v w b y y1 C L K E2 8 5 D2 0 1 scale Dimensions Unit mm 2 mm A(1) A1 A2 max 0.80 0.05 0.65 nom 0.75 0.02 0.55 min 0.70 0.00 0.45 A3 b D(1) D2 E(1) E2 0.2 0.
PAGE 47
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
PAGE 48
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 13.
PAGE 49
SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 42. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 35.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD Table 35. Abbreviations …continued Acronym Description SMBus System Management Bus SO-DIMM Small Outline Dual In-line Memory Module SPD Serial Presence Detect 15. Revision history Table 36. Revision history Document ID Release date Data sheet status Change notice Supersedes SE97B_1 20100127 Product data sheet - - SE97B_1 Product data sheet © NXP B.V. 2010. All rights reserved. Rev.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 18. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 Temperature sensor features . . . . . . . . . . . . . . 2 Serial EEPROM features . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . .
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SE97B NXP Semiconductors DDR memory module temp sensor with integrated SPD 17 18 Contact information. . . . . . . . . . . . . . . . . . . . . 51 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.