Freescale Semiconductor Technical Data Document Number: SGTL5000 Rev. 6.0, 11/2013 Low Power Stereo Codec with Headphone Amp SGTL5000 The SGTL5000 is a Low Power Stereo Codec with Headphone Amp from Freescale, and is designed to provide a complete audio solution for products needing LINEIN, MIC_IN, LINEOUT, headphone-out, and digital I/O. Deriving it’s architecture from best in class, Freescale integrated products that are currently on the market.
INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM Analog Gain LINE_IN MIC_IN Analog Gain (0 to 22.5dB) MIC GAIN (0dB, 20dB, 30dB, 40dB ) Digital Gain DAC Volume Control -90dB to 0dB ADC DAC Headphone Volume Control -52dB to +12dB (CHIP_ANA_HP_CTRL) HP_OUT Audio Switch I2S_DIN Line Out Volume Control (CHIP_LINE_OUT_VOL) I2S_DOUT Mix +6dB AVC +12dB Surround Bass Enhancement +6dB LINEOUT Tone Control /GEQ/PEQ +12dB Only Gain is shown for the Digital Audio Processing blocks.
PIN CONNECTIONS 2 14 I2S_LRCLK VDDA 3 13 SYS_MCLK HP_L 4 12 VDDIO VAG 5 11 MIC_BIAS 6 7 8 9 10 LINEOUT_R LINEOUT_L LINEIN_R LINEIN_L MIC GND CTRL_CLK NC CTRL_DATA I2S_DIN I2S_DOUT 28 27 26 25 GND 1 24 I2S_SCLK HP_R 2 23 I2S_LRCLK GND 3 22 NC HP_VGND 4 VDDA 5 20 VDDIO HP_L 6 19 NC AGND 7 18 CPFILT NC 8 17 NC 21 SYS_MCLK GND 9 10 20 QFN Transparent Top View 11 12 13 14 15 16 MIC_BIAS HP_VGND 29 MIC I2S_SCLK 30 LINEIN_L 15 31 LINEIN_
PIN CONNECTIONS Table 1.
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings Exceeding the absolute maximum ratings shown in the following table could cause permanent damage to the part and is not recommended. Normal operation is not guaranteed at the absolute maximum ratings, and extended exposure could affect long term reliability. Ratings Symbol Value Unit Maximum Digital Voltage VDDD 1.98 V Maximum Digital I/O Voltage VDDIO 3.
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 4. Input/Output Electrical Characteristics Test Conditions unless otherwise noted: VDDIO = 3.3 V, VDDA = 3.3 V, TA = 25 °C, Slave mode, fS = 48 kHz, MCLK = 256 fS, 24 bit input, 1.02 kHz sine. Characteristic Symbol Min Typ Max Unit LINEIN Input Level (3.3 V VDDA) - - 2.83 VPP LINEIN Input Level (1.8 V VDDA) - - 1.60 VPP MIC Input Level (3.3 V VDDA) - - 2.83 VPP MIC Input Level (1.8 V VDDA) - - 1.60 VPP 1.46 1.52 1.68 2.53 2.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Audio Performance 1 Test Conditions unless otherwise noted: VDDIO = 1.8 V, VDDA = 1.8 V, TA = 25 °C, Slave mode, fS = 48 kHz, MCLK = 256 fS, 24 bit input Characteristic Symbol Min Typ Max Unit LINEIN Input Level - 0.57 - VRMS LINEIN Input Impedance (at 1.02 kHz) - 29 - k SNR (-60 dB input) - 85 - dB THD+N - -70 - dB Frequency Response - 0.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 6. Audio Performance 2 Test Conditions unless otherwise noted: VDDIO = 3.3 V, VDDA = 3.3 V, TA = 25°C, Slave mode, fS = 48 kHz, MCLK = 256 fS, 24 bit input. ADC tests were conducted with BIAS_CTRL = -37.5%, all other tests conducted with BIAS_CTRL = -50%. Characteristic Symbol Min Typ Max Unit LINEIN Input Level - 1.0 - VRMS LINEIN Input Impedance (at 1.
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 7. Dynamic Electrical Characteristics Characteristic Symbol Min Typ Max Unit tPC 1.
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Tpc VDDA VDDIO VDDD (if used) SYS_MCLK CTRL_DATA CTRL_CLK CTRL_ADR0_CS Initial Communication Figure 4. Power Up Timing 1/Fi2c_clk Ti2cdsu Ti2cclkh Ti2cclkl CTRL_CLK Ti2cstsu Ti2cdh Ti2csh CTRL_DATA Figure 5. I2C Timing (CTRL_MODE == 0) Tcsl Tcsh CTRL_ADR0_CS CTRL_AD0_CS 1/Fspi_clk Tspiclkh Tspiclkl Tccs Tcsc CTRL_CLK Tspidsu Tspidh CTRL_DATA Figure 6.
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS . Ti2s_s 1/Fsclk I2S_SCLK I2S_LRCLK In slave mode Ti2s_d I2S_LRCLK In master mode Ti2s_s Ti2s_h I2S_SCLK I2S_DIN Ti2s_d I2S_DOUT 1/Flrclk I2S_LRCLK Figure 7.
FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The SGTL5000 is a low power stereo codec with integrated headphone amplifier. It is designed to provide a complete audio solution for portable products needing LINEIN, mic-in, LINEOUT, headphone-out, and digital I/O.
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION POWER The SGTL5000 has a flexible power architecture to allow the system designer to minimize power consumption and maximize performance at the lowest cost. External Power Supplies The SGTL5000 requires 2 external power supplies: VDDA and VDDIO. An optional third external power supply VDDD may be provided externally to achieve lower power. This external VDDD power supply is required for new designs.
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Table 8. Synchronous MCLK Rates and Sampling Frequencies CLOCK SUPPORTED RATES System Master Clock (SYS_MCLK) UNITS 256, 384, 512 Sampling Frequency (Fs) Fs 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 96 (6) kHz Notes 6. For a sampling frequency of 96 kHz, only 256 Fs SYS_MCLK is supported Using the PLL - Asynchronous SYS_MCLK input An integrated PLL is provided in the SGTL5000 that allows any clock from 8.
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION To configure a route, the CHIP_SSS_CTRL register is used. Each output from the source select switch has its own register field that is used to select what input is routed to that output. For example, to route the I2S digital input through the DAP and then out to the DAC (headphone) outputs write SSS_CTRL->DAP_SELECT to 0x1 (selects I2S_IN) and SSS_CTRL->DAC_SELECT to 0x3 (selects DAP output).
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Line Outputs The SGTL5000 contains a stereo line output. The line output has a dedicated gain stage that can be used to adjust the output level. The CHIP_LINE_OUT_VOL controls the line level output gain. The line outputs also have a dedicated mute that is controlled by the register field CHIP_ANA_CTRL>MUTE_LO. The line out volume is intended as maximum output level adjustment. It is intended to be used to set the maximum output swing.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL DEVICE OPERATION POWER CONSUMPTION Table 9. Power Consumption: VDDA=1.8 V, VDDIO=1.8 V CURRENT CONSUMPTION (MA) MODE POWER (MW) VDDD VDDA VDDIO Playback (I2S->DAC->Headphone) - 2.54 0.9 6.19 Playback with DAP ((I2S->DAP->DAC->Headphone) - 3.59 0.9 8.08 Playback/Record (I2S->DAC->Headphone, ADC->I2S) - 3.71 1.10 8.67 Record (ADC->I2S) - 2.29 1.06 6.02 Analog playback, CODEC bypassed (LINEIN->HP) - 1.48 0.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION the left subframe should always be presented first regardless of the CHIP_I2S_CTRL->LRPOL setting. The I2S_LRCLK and I2S_SCLK can be programmed as master (driven to an external target) or slave (driven from an external source). When the clocks are in slave mode, they must be synchronous to SYS_MCLK. For this reason the SGTL5000 can only operate in synchronous mode (see Clocking) while in I2S slave mode.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION PCM Mode frame clock may be configured to clock in on the rising or falling edge of Bit Clock. PCM Format A is a format in which the data word begins one SCLK bit following the I2S_LRCLK transition, as in I2S Mode. PCM Format B is a format in which the data word begins after the I2S_LRCLK transition, as in Left Justified. In slave mode, the pulse width of the I2S_LRCLK does not matter.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Set DAP_CONTROL->DAP_EN to enable DAP block 7-Band Parametric EQ From Source Select Swtich Main Input Mix Input Automatic Automatic Volume Volume Control Control (AVC) (AVC) Dual Dual Input Input Mixer Mixer Freescale SigmaTel Bass Bass Enhance Enhance SigmaTel Freescale Surround Surround 5-Band Graphic EQ To Source Select Swtich Tone Control Each DAP sub-block can be configured in a pass-through mode Only one of PEQ/GEQ/TC can b
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION Input Output SigmaTel Freescale Surround Surround From Dual Mixer To Freescale BassEnhance Enhance To SGTL Bass DAP_SGTL_SURROUND -> WIDTH_CONTROL ->SELECT The Freescale Surround can be enabled or configured in pass-through mode (input is passed through without any processing). When enabling the Surround, mono or stereo input type must be selected based on the input signal. Surround width may be adjusted for the size of the sound stage.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION H ( z) b0 b1 z 1 b2 z 2 1 a1 z 1 a2 z 2 Direct Form 1 X(z) H(z)X(z) b0 z 1 z 1 b1 -a1 z 1 z 1 b2 -a2 Figure 15. 5-Coefficient Biquad Filter and Transfer Function If a band is enabled but is not being used (flat response), then a value of 0.5 should be put in b0 and all other coefficients should be set to 0.0. Note that the coefficients must be converted to hex values before writing to the registers.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION DAP_AVC_THRESHOLD Input from Dual Input Mixer If < Threshold Decay (0.05dB/s to ~200dB/s) DAP_AVC_DECAY DAP_AVC_THRESHOLD -> MAX_GAIN Threshold Level Compare Volume Control Output To to Output Freescale Surround SGTL Surround If > Threshold Attack (0.8dB/s to ~3200dB/s) DAP_AVC_ATTACK Figure 16. DAP AVC Block Diagram When the measured audio level is below threshold, the AVC can apply a maximum gain of up to 12 dB.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION I2C Address R/W ACK A15 A8 ACK A7 A0 ACK D15 D8 ACK Start Condition D7 D0 ACK Stop Condition Figure 17. Functional I2C Diagram The protocol has an auto increment feature. Instead of sending the stop condition after two bytes of data, the master may continue to send data byte pairs for writing, or it may send extra clocks for reading data byte pairs.
FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION On rising edge of SS, latch the last 32 bits of data 16-bits Register Value 16-bits Register Address SS 23 31 7 15 0 SCK MOSI Addr 15 Addr 14 Addr 8 Addr 7 Addr 6 Addr 0 Val 15 Val 14 Val 8 Val 7 Val 6 Val 0 Figure 18.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES PROGRAMMING EXAMPLES This section provides programming examples showing how to configure the chip. The registers can be written/read by using I2C communication protocol. The chip also supports SPI communication protocol (not supported in the 20 QFN package), but only register write operation is supported. PROTOTYPE FOR READING AND WRITING A REGISTER The generic register read write prototype is used throughout this section, as shown by the following.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Write CHIP_ANA_CTRL 0x0133 //------------Power up Inputs/Outputs/Digital Blocks--------// Power up LINEOUT, HP, ADC, DAC Write CHIP_ANA_POWER 0x6AFF // Power up desired digital blocks // I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5), // ADC (bit 6) are powered on Write CHIP_DIG_POWER 0x0073 Modify CHIP_PLL_CTRL->FRAC_DIVISOR Frac_Divisor // bits 10:0 Input/Output Routing To avoid any pops/clicks, the outputs should be muted during these chip
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES // Configure the surround width // (0x0 = Least width, 0x7 = Most width). This example shows // a width setting of 5 Modify DAP_SGTL_SURROUND->WIDTH_CONTROL 0x0005 // bits 6:4 Freescale Bass Enhance The Freescale Bass Enhance on/off function is typically controlled by the end-user. End-user driven programming steps are shown in End-user Driven Chip Configuration.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES END-USER DRIVEN CHIP CONFIGURATION End-users control features like volume up/down, and audio EQ parameters such as Bass and Treble. This requires programming the chip without introducing any pops/clicks or any other disturbance to the output. This section shows examples on how to program these features. VOLUME AND MUTE CONTROL Refer to Volume Control for examples on how to program volume when end-user changes the volume or mutes/ unmutes the output.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES // SELECT bits 1:0 { Modify DAP_SGTL_SURROUND->SELECT 0x0003; ++usNextVal; // Ramp down the width to original value for (int i = 0; i++; (7 - usOriginalVal) Modify DAP_BASS_ENHANCE_CTRL->BASS_LEVEL usNextVal; { } --usNextVal; // Enable (To disable, write 0x0000) Bass Enhance Modify DAP_SGTL_SURROUND->WIDTH_CONTROL usNextVal; // EN bit 0 } // Ramp Bass level back to original value Modify DAP_BASS_ENHANCE->EN 0x0001; for (int i = 0; i++; usNumSte
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 5 DAC_POWERUP RW 0x0 DEFINITION Enable/disable the DAC block, both analog and digital 0x0 = Disable 0x1 = Enable 4 DAP_POWERUP RW 0x0 Enable/disable the DAP block 0x0 = Disable 0x1 = Enable 3:2 RSVD RW 0x0 Reserved 1 I2S_OUT_POWERUP RW 0x0 Enable/disable the I2S data output 0x0 = Disable 0x1 = Enable 0 I2S_IN_POWERUP RW 0x0 Enable/disable the I2S data input 0x0 = Disable 0x1 = Enable Table 18.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 19. CHIP_I2S_CTRL 0x0006 12 11 10 9 8 RSVD 7 MS 6 5 4 DLEN 3 2 I2S_MODE 1 LRALIGN 13 SCLK_INV 14 SCLKFREQ 15 0 LRPOL BITS FIELD RW RESET DEFINITION 15:9 RSVD RO 0x0 Reserved 8 SCLKFREQ RW 0x0 Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave mode (MS=0), this field must be set appropriately to match SCLK input rate.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 20. CHIP_SSS_CTRL 0x000A 10 RSVD 9 8 DAP_MIX_SELECT 11 I2S_LRSWAP 12 DAC_LRSWAP 13 DAP_LRSWAP RSVD 14 DAP_MIX_LRSWAP 15 7 6 DAP_SELECT BITS FIELD RW RESET 15 RSVD RW 0x0 Reserved 14 DAP_MIX_LRSWAP RW 0x0 DAP Mixer Input Swap 5 4 3 DAC_SELECT 2 RSVD 1 0 I2S_SELECT DEFINITION 0x0 = Normal Operation 0x1 = Left and Right channels for the DAP MIXER Input are swapped.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 21.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 22. CHIP_DAC_VOL 0x0010 15 14 13 12 11 10 9 8 7 6 5 DAC_VOL_RIGHT 4 3 2 1 0 DAC_VOL_LEFT BITS FIELD RW RESET 15:8 DAC_VOL_RIGHT RW 0x3C DEFINITION DAC Right Channel Volume Set the Right channel DAC volume with 0.5017 dB steps from 0 to -90 dB 0x3B and less = Reserved 0x3C = 0 dB 0x3D = -0.5 dB 0xF0 = -90 dB 0xFC and greater = Muted If VOL_RAMP_EN = 1, there is an automatic ramp to the new volume setting.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD 5:4 RW I2S_DOUT RW RESET 0x1 DEFINITION 2 I S DOUT Pad Drive Strength Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 3.3 V 0x0 = Disable 3:2 CTRL_DATA RW 0x3 0x1 = 1.66 mA 2.87 mA 4.02 mA 0x2 = 3.33 mA 5.74 mA 8.03 mA 0x3 = 4.99 mA 8.61 mA 12.05 mA I2C DATA Pad Drive Strength Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 3.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 7:4 ADC_VOL_RIGHT RW 0x0 DEFINITION ADC Right Channel Volume Right channel analog ADC volume control in 1.5.0 dB steps. 0x0 = 0 dB 0x1 = +1.5 dB ... 0xF = +22.5 dB This range is -6.0 dB to +16.5 dB if ADC_VOL_M6DB is set to 1. 3:0 ADC_VOL_LEFT RW 0x0 ADC Left Channel Volume Left channel analog ADC volume control in 1.5 dB steps. 0x0 = 0 dB 0x1 = +1.5 dB ... 0xF = +22.5 dB This range is -6.0 dB to +16.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 26. 7.0.0.11. CHIP_ANA_CTRL 0x0024 8 MUTE_LO RSVD 9 BITS FIELD RW RESET 15:9 RSVD RO 0x0 Reserved 8 MUTE_LO RW 0x1 LINEOUT Mute 7 RSVD 6 5 4 3 RSVD 2 1 0 MUTE_ADC 10 EN_ZCD_ADC 11 SELECT_ADC 12 MUTE_HP 13 EN_ZCD_HP 14 SELECT_HP 15 DEFINITION 0x0 = Unmute 0x1 = Mute 7 RSVD RO 0x0 Reserved 6 SELECT_HP RW 0x0 Select the headphone input.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 27. CHIP_LINREG_CTRL 0x0026 14 13 12 11 10 9 8 7 VDDC_MAN_ASSN RSVD 6 5 VDDC_ASSN_OVRD 15 4 3 RSVD 2 1 0 D_PROGRAMMING BITS FIELD RW RESET DEFINITION 15:7 RSVD RO 0x0 Reserved 6 VDDC_MAN_ASSN RW 0x0 Determines chargepump source when VDDC_ASSN_OVRD is set.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 3:1 BIAS_CTRL RW 0x0 DEFINITION Bias control These bits adjust the bias currents for all of the analog blocks. By lowering the bias current a lower quiescent power is achieved. It should be noted that this mode can affect performance by 3-4 dB. 0x0 = Nominal 0x1-0x3=+12.5% 0x4=-12.5% 0x5=-25% 0x6=-37.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 30. CHIP_LINE_OUT_CTRL 0x002C 15 14 13 12 11 RSVD 10 9 8 7 OUT_CURRENT 6 5 4 RSVD 3 2 1 0 LO_VAGCNTRL BITS FIELD RW RESET DEFINITION 15:12 RSVD RO 0x0 Reserved 11:8 OUT_CURRENT RW 0x0 Controls the output bias current for the LINEOUT amplifiers. The nominal recommended setting for a 10 k load with 1.0 nF load cap is 0x3. There are only 5 valid settings. 0x0=0.18 mA, 0x1=0.27 mA, 0x3=0.36 mA, 0x7=0.45 mA, 0xF=0.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES The Table 33, CHIP_ANA_POWER 0x0030 register contains all of the power down controls for the analog blocks. The only other power-down controls are BIAS_RESISTOR in the MIC_CTRL register and the EN_ZCD control bits in ANA_CTRL. Table 33.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 8 VCOAMP_POWERUP RW 0x0 DEFINITION Power up the PLL VCO amplifier. 0x0 = Power down 0x1 = Power up 7 VAG_POWERUP RW 0x0 Power up the VAG reference buffer. Setting this bit starts the power up ramp for the headphone and LINEOUT. The headphone (and/or LINEOUT) powerup should be set BEFORE clearing this bit. When this bit is cleared the power-down ramp is started.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES The Table 34, CHIP_PLL_CTRL 0x0032 register may only be changed after reset, and before PLL_POWERUP is set. Table 34. CHIP_PLL_CTRL 0x0032 15 14 13 12 11 10 9 8 7 INT_DIVISOR 6 5 4 3 2 1 0 FRAC_DIVISOR BITS FIELD RW RESET DEFINITION 15:11 INT_DIVISOR RW 0xA This is the integer portion of the PLL divisor.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 3 INPUT_FREQ_DIV2 RW 0x0 DEFINITION SYS_MCLK divider before PLL input 0x0 = pass through 0x1 = SYS_MCLK is divided by 2 before entering PLL This must be set when the input clock is above 17 MHz. This has no effect when the PLL is powered down. 2:0 RSVD RW Reserved 0x0 Status bits for analog blocks are found in Table 36, CHIP_ANA_STATUS 0x0036 Table 36.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW 15:14 HP_IALL_ADJ RW RESET DEFINITION 0x0 These bits control the overall bias current of the headphone amplifier (all stages including first and output stage). 0x0=nominal, 0x1=-50%, 0x2=+50%, 0x3=-40% 13:12 HP_I1_ADJ RW 0x0 These bits control the bias current for the first stage of the headphone amplifier.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET DEFINITION 10 LO_PASS_MASTERV AG RW 0x0 Tie the main analog VAG to the LINEOUT VAG. This can improve SNR for the LINEOUT when both are the same voltage. 9 INVERT_DAC_SAMPL E_CLOCK RW 0x0 Change the clock edge used for the DAC output sampling. 8 INVERT_DAC_DATA_ TIMING RW 0x0 Change the clock edge used for the digital to analog DAC data crossing. 7 DAC_EXTEND_RTZ RW 0x0 Extend the return-to-zero time for the DAC.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET DEFINITION 10:8 LVLADJL RW 0x0 These bits adjust the sensitivity of the left channel headphone short detector in 25 mA steps.This trip point can vary by ~30% over process so leave plenty of guard band to avoid false trips. This short detect trip point is also effected by the bias current adjustments made by CHIP_REF_CTRL -> BIAS_CTRL and by CHIP_ANA_TEST1 > HP_IALL_ADJ.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 40. DAP_CONTROL 0x0100 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 2 MIX_EN BITS FIELD RW RESET 15:5 RSVD RO 0x0 Reserved 4 MIX_EN RW 0x0 Enable/Disable the DAP mixer path 1 0 RSVD DAP_EN DEFINITION 0x0 = Disable 0x1 = Enable When enabled, DAP_EN must also be enabled to use the mixer. 3:1 RSVD RO 0x0 Reserved 0 DAP_EN RW 0x0 Enable/Disable digital audio processing (DAP) 0x0 = Disable.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES BITS FIELD RW RESET 6:4 CUTOFF RW 0x4 DEFINITION Set cut-off frequency 0x0 = 80 Hz 0x1 = 100 Hz 0x2 = 125 Hz 0x3 = 150 Hz 0x4 = 175 Hz 0x5 = 200 Hz 0x6 = 225 Hz 3:1 RSVD RO 0x0 Reserved 0 EN RW 0x0 Enable/Disable Bass Enhance 0x0 = Disable 0x1 = Enable Table 43.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 45. DAP_SGTL_SURROUND 0x010A 15 14 13 12 11 10 9 8 7 RSVD 6 5 4 3 WIDTH_CONTROL 2 RSVD 1 0 SELECT BITS FIELD RW RESET DEFINITION 15:7 RSVD RO 0x0 Reserved 6:4 WIDTH_CONTROL RW 0x4 Freescale Surround Width Control - The width control changes the perceived width of the sound field. 0x0 = Least Width ......
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 47.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 49. DAP_AUDIO_EQ_BASS_BAND0 0x0116 115 Hz 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 2 1 0 2 1 0 2 1 0 VOLUME BITS FIELD RW RESET 15:7 RSVD RO 0x0 6:0 VOLUME RW 0x2F DEFINITION Reserved Sets Tone Control Bass/GEQ Band0 0x5F = sets to 12 dB 0x2F = sets to 0 dB 0x00 = sets to -11.75 dB Each LSB is 0.25 dB Table 50.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 52. DAP_AUDIO_EQ_BAND3 0x011C 3000 Hz 15 14 13 12 11 10 9 8 7 6 5 4 3 RSVD 2 1 0 VOLUME BITS FIELD RW RESET 15:7 RSVD RO 0x0 6:0 VOLUME RW 0x2F DEFINITION Reserved Sets GEQ Band3 0x5F = sets to 12 dB 0x2F = sets to 0 dB 0x00 = sets to -11.75 dB Each LSB is 0.25 dB Table 53.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 56. DAP_AVC_CTRL 0x0124 14 RSVD RSVD 13 12 11 MAX_GAIN 10 RSVD 9 8 7 LBI_RESPONSE 6 RSVD 5 4 3 HARD_LIMIT_EN 15 2 1 0 RSVD EN BITS FIELD RW RESET DEFINITION 15 RSVD RO 0x0 Reserved 14 RSVD RW 0x1 Reserved. 13:12 MAX_GAIN RW 0x1 Maximum gain that can be applied by the AVC in expander mode. 0x0 = 0 dB gain 0x1 = 6.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 58. DAP_AVC_ATTACK 0x0128 15 14 13 12 11 10 9 8 7 6 RSVD 5 4 3 2 1 0 RATE BITS FIELD RW RESET DEFINITION 15:12 RSVD RO 0x0 Reserved 11:0 RATE RW 0x28 AVC Attack Rate This is the rate at which the AVC applies attenuation to the signal to bring it to the threshold level. AVC Attack Rate is programmable.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 61. DAP_COEF_WR_B1_LSB 0x012E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSVD 1 0 LSB BITS FIELD RW RESET DEFINITION 15:4 RSVD RO 0x0 Reserved 3:0 LSB RW 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. Table 62.
FUNCTIONAL DEVICE OPERATION PROGRAMMING EXAMPLES Table 67. DAP_COEF_WR_A2_LSB 0x013A 15 14 13 12 11 10 9 8 7 6 5 4 RSVD 3 2 1 0 LSB BITS FIELD RW RESET DEFINITION 15:4 RSVD RO 0x0 Reserved 3:0 LSB RW 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written.
TYPICAL APPLICATIONS INTRODUCTION TYPICAL APPLICATIONS INTRODUCTION connected to a 0.1 F cap to GND. If either is > 3.0 V, the CPFILT cap MUST NOT be placed. HP_VGND Note: Do not connect HP_VGND to system ground, even when unused. This is a virtual ground (DC voltage) that should never connect to an actual “0 Volt ground”. Use the widest, shortest trace possible for the HP_VGND. Typical connections are shown in the following application diagrams.
TYPICAL APPLICATIONS INTRODUCTION VDDD (1.1V - 2.0V, 11mA Min) Note: External VDDD required for new designs. I2C_CLK I2C_DATA C1 I2S_DIN I2SDOUT I2S_SCLK I2S_LRCLK 0.1uF 20 19 18 17 16 U1 J1 2 3 4 5 1 C2 220uF C3 220uF VDDD CTRL_CLK CTRL_DATA I2S_DIN I2S_DOUT Note: Cap-coupled headphone design shown here. For capless design, see 32QFN Typical Application Schematic.
PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed on the following pages.
PACKAGING PACKAGE DIMENSIONS EP SUFFIX 20-PIN 98ARE10742D REVISION 0 SGTL5000 62 Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS EP SUFFIX 20-PIN 98ARE10742D REVISION 0 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 63
PACKAGING PACKAGE DIMENSIONS FC SUFFIX 32-PIN 98ARE10739D REVISION 0 SGTL5000 64 Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS FC SUFFIX 32-PIN 98ARE10739D REVISION 0 SGTL5000 Analog Integrated Circuit Device Data Freescale Semiconductor 65
PACKAGING PACKAGE DIMENSIONS FC SUFFIX 32-PIN 98ARE10739D REVISION 0 SGTL5000 66 Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION 3.0 6/2010 • 4.0 9/2010 • Corrected Pin 4 explanation (32-pin package) and added Pin 3 (32-Pin package) to Table 1. 5/2013 • • • • • • Corrected LINEOUT - 100 dB SNR (-60 dB input) and -85 dB THD+N (VDDIO = 3.3 V) in features Added note for HP_VGND and CPFILT in pin definition table Moved Recommended Operating Conditions to separate table Added Input/Output Electrical Characteristics Corrected LINEIN Input Level from 0.75 to 0.
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