INTEGRATED CIRCUITS DATA SHEET SJA1000 Stand-alone CAN controller Product specification Supersedes data of 1999 Aug 17 File under Integrated Circuits, IC18 2000 Jan 04
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 6.2.1 6.2.
Philips Semiconductors Product specification Stand-alone CAN controller 1 SJA1000 FEATURES 2 • Pin compatibility to the PCA82C200 stand-alone CAN controller GENERAL DESCRIPTION The SJA1000 is a stand-alone controller for the Controller Area Network (CAN) used within automotive and general industrial environments. It is the successor of the PCA82C200 CAN controller (BasicCAN) from Philips Semiconductors. Additionally, a new mode of operation is implemented (PeliCAN) which supports the CAN 2.
Philips Semiconductors Product specification Stand-alone CAN controller 4 SJA1000 BLOCK DIAGRAM handbook, full pagewidth ALE/AS, CS, RD/E, WR, CLKOUT, MODE, INT 22 3 to 7, 11, 16 SJA1000 8 VDD1 VSS1 control 7 8 address/data INTERFACE MANAGEMENT LOGIC AD7 to AD0 2, 1, 28 to 23 internal bus 12 15 13 MESSAGE BUFFER BIT STREAM PROCESSOR TRANSMIT BUFFER BIT TIMING LOGIC 14 19 20 21 18 RECEIVE FIFO RECEIVE BUFFER XTAL1 XTAL2 ACCEPTANCE FILTER VSS3 TX0 TX1 RX0 RX1 VSS2 VDD2 ERROR MANAGEME
Philips Semiconductors Product specification Stand-alone CAN controller 5 SJA1000 PINNING SYMBOL AD7 to AD0 PIN 2, 1, 28 to 23 DESCRIPTION multiplexed address/data bus ALE/AS 3 ALE input signal (Intel mode), AS input signal (Motorola mode) CS 4 chip select input, LOW level allows access to the SJA1000 RD/E 5 RD signal (Intel mode) or E enable signal (Motorola mode) from the microcontroller WR 6 WR signal (Intel mode) or RD/WR signal (Motorola mode) from the microcontroller CLKOUT 7 clo
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, halfpage handbook, halfpage AD6 1 28 AD5 AD6 1 28 AD5 AD7 2 27 AD4 AD7 2 27 AD4 ALE/AS 3 26 AD3 ALE/AS 3 26 AD3 CS 4 25 AD2 CS 4 25 AD2 RD/E 5 24 AD1 RD/E 5 24 AD1 WR 6 23 AD0 WR 6 23 AD0 22 VDD1 CLKOUT 7 SJA1000T 21 VSS2 VSS1 8 21 VSS2 VSS1 8 XTAL1 9 20 RX1 XTAL1 9 20 RX1 XTAL2 10 19 RX0 XTAL2 10 19 RX0 MODE 11 18 VDD2 MODE 11 18 VDD2 VDD3 12 VDD3 12 17 RST 17 RST TX
Philips Semiconductors Product specification Stand-alone CAN controller 6 SJA1000 oscillator drifts) and to define the sample point and the number of samples to be taken within a bit time. FUNCTIONAL DESCRIPTION 6.1 6.1.1 Description of the CAN controller blocks 6.1.7 INTERFACE MANAGEMENT LOGIC (IML) The interface management logic interprets commands from the CPU, controls addressing of the CAN registers and provides interrupts and status information to the host microcontroller. 6.1.
Philips Semiconductors Product specification Stand-alone CAN controller 6.2.1.3 SJA1000 Receive buffer 6.3 6.3.1 The dual receive buffer concept of the PCA82C200 is replaced by the receive FIFO from the PeliCAN controller. This has no effect to the application software except for the data overrun probability. Now more than two messages may be received (up to 64 bytes) until a data overrun occurs. 6.2.1.4 The address area of the SJA1000 consists of the control segment and the message buffers.
Philips Semiconductors Product specification Stand-alone CAN controller Table 1 SJA1000 BasicCAN address allocation; note 1 CAN ADDRESS 0 OPERATING MODE RESET MODE SEGMENT READ control 1 WRITE READ WRITE control control control control (FFH) command (FFH) command 2 status − status − 3 interrupt − interrupt − 4 (FFH) − acceptance code acceptance code 5 (FFH) − acceptance mask acceptance mask 6 (FFH) − bus timing 0 bus timing 0 7 (FFH) − bus timing 1 bus timin
Philips Semiconductors Product specification Stand-alone CAN controller 6.3.2 SJA1000 RESET VALUES Detection of a ‘reset request’ results in aborting the current transmission/reception of a message and entering the reset mode. On the ‘1-to-0’ transition of the reset request bit, the CAN controller returns to the operating mode. Table 2 Reset mode configuration; notes 1 and 2 VALUE REGISTER Control Command Status Interrupt 2000 Jan 04 BIT SYMBOL NAME RESET BY HARDWARE SETTING BIT CR.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 VALUE REGISTER BIT SYMBOL NAME RESET BY HARDWARE SETTING BIT CR.0 BY SOFTWARE OR DUE TO BUS-OFF Acceptance code AC.7 to 0 AC Acceptance Code X X Acceptance mask AM.7 to 0 AM Acceptance Mask X X Bus timing 0 Bus timing 1 Output control BTR0.7 SJW.1 Synchronization Jump Width 1 X X BTR0.6 SJW.0 Synchronization Jump Width 0 X X BTR0.5 BRP.5 Baud Rate Prescaler 5 X X BTR0.4 BRP.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Notes 1. X means that the value of these registers or bits is not influenced. 2. Remarks in brackets explain functional meaning. 3. Reading the command register will always reflect a binary ‘11111111’. 4. On bus-off the error interrupt is set, if enabled. 5. Internal read/write pointers of the RXFIFO are reset to their initial values.
Philips Semiconductors Product specification Stand-alone CAN controller BIT SYMBOL CR.1 RIE CR.
Philips Semiconductors Product specification Stand-alone CAN controller Table 4 SJA1000 Bit interpretation of the command register (CMR); CAN address 1 BIT SYMBOL NAME VALUE FUNCTION CMR.7 − − − reserved CMR.6 − − − reserved CMR.5 − − − reserved CMR.
Philips Semiconductors Product specification Stand-alone CAN controller 6.3.5 SJA1000 STATUS REGISTER (SR) The content of the status register reflects the status of the SJA1000. The status register appears to the microcontroller as a read only memory. Table 5 Bit interpretation of the status register (SR); CAN address 2 BIT SR.7 SYMBOL BS NAME Bus Status; note 1 SR.6 ES Error Status; note 2 SR.5 TS Transmit Status; note 3 SR.4 SR.3 SR.2 SR.1 SR.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Notes 1. When the transmit error counter exceeds the limit of 255 [the bus status bit is set to logic 1 (bus-off)] the CAN controller will set the reset request bit to logic 1 (present) and an error interrupt is generated, if enabled. It will stay in this mode until the CPU clears the reset request bit.
Philips Semiconductors Product specification Stand-alone CAN controller 6.3.6 SJA1000 INTERRUPT REGISTER (IR) The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, the INT pin is activated (LOW). After this register is read by the microcontroller, all bits are reset what results in a floating level at INT. The interrupt register appears to the microcontroller as a read only memory.
Philips Semiconductors Product specification Stand-alone CAN controller 6.3.7 SJA1000 TRANSMIT BUFFER LAYOUT The global layout of the transmit buffer is shown in Table 7. The buffer serves to store a message from the microcontroller to be transmitted by the SJA1000. It is subdivided into a descriptor and data field. The transmit buffer can be written to and read out by the microcontroller in operating mode only. In reset mode a ‘FFH’ is reflected for all bytes.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth 64-byte FIFO message 3 message 2 release receive buffer command message 1 incoming messages 29 28 27 26 25 24 23 22 21 20 receive buffer window CAN address MGK618 Message 1 is now available in the receive buffer. Fig.4 Example of the message storage within the RXFIFO.
Philips Semiconductors Product specification Stand-alone CAN controller 6.3.9.1 Table 8 SJA1000 Acceptance Code Register (ACR) ACR bit allocation; can address 4 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 AC.7 AC.6 AC.5 AC.4 AC.3 AC.2 AC.1 AC.0 This register can be accessed (read/write), if the reset request bit is set HIGH (present).
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 10 PeliCAN address allocation; note 1 OPERATING MODE CAN ADDRESS RESET MODE READ WRITE READ WRITE 0 mode mode mode mode 1 (00H) command (00H) command 2 status − status − 3 interrupt − interrupt − 4 interrupt enable interrupt enable interrupt enable interrupt enable 5 reserved (00H) − reserved (00H) − 6 bus timing 0 − bus timing 0 bus timing 0 7 bus timing 1 − bus timing 1 b
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 OPERATING MODE CAN ADDRESS READ RESET MODE WRITE READ WRITE 27 (FIFO RAM); note 5 RX data 7 − TX data 7 reserved (00H) − 28 (FIFO RAM); note 5 RX data 8 − TX data 8 reserved (00H) − 29 RX message counter − RX message counter − 30 RX buffer start address − RX buffer start address RX buffer start address 31 clock divider clock divider; note 6 clock divider clock divider 32 internal RAM addre
Philips Semiconductors Product specification Stand-alone CAN controller 6.4.2 SJA1000 RESET VALUES Detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. On the ‘1-to-0’ transition of the reset mode bit, the CAN controller returns to the mode defined within the mode register.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 VALUE REGISTER Interrupt enable Bus timing 0 Bus timing 1 2000 Jan 04 BIT SYMBOL NAME RESET BY HARDWARE SETTING MOD.0 BY SOFTWARE OR DUE TO BUS-OFF IER.7 BEIE Bus Error Interrupt Enable X X IER.6 ALIE Arbitration Lost Interrupt Enable X X IER.5 EPIE Error Passive Interrupt Enable X X IER.4 WUIE Wake-Up Interrupt Enable X X IER.3 DOIE Data Overrun Interrupt Enable X X IER.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 VALUE REGISTER Output control BIT SYMBOL NAME RESET BY HARDWARE SETTING MOD.0 BY SOFTWARE OR DUE TO BUS-OFF OCR.7 OCTP1 Output Control Transistor P1 X X OCR.6 OCTN1 Output Control Transistor N1 X X OCR.5 OCPOL1 Output Control Polarity 1 X X OCR.4 OCTP0 Output Control Transistor P0 X X OCR.3 OCTN0 Output Control Transistor N0 X X OCR.2 OCPOL0 Output Control Polarity 0 X X OCR.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Notes 1. X means that the value of these registers or bits is not influenced. 2. Remarks in brackets explain functional meaning. 3. On bus-off the error warning interrupt is set, if enabled. 4.
Philips Semiconductors Product specification Stand-alone CAN controller BIT SYMBOL NAME MOD.1 LOM Listen Only Mode; notes 2 and 3 MOD.
Philips Semiconductors Product specification Stand-alone CAN controller 6.4.4 SJA1000 COMMAND REGISTER (CMR) A command bit initiates an action within the transfer layer of the CAN controller. This register is write only, all bits will return a logic 0 when being read. Between two commands at least one internal clock cycle is needed in order to proceed. The internal clock is half of the external oscillator frequency.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 5. The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either transmitted successfully or aborted, the transmission complete status bit should be checked.
Philips Semiconductors Product specification Stand-alone CAN controller BIT SR.1 SR.0 SYMBOL DOS RBS NAME Data Overrun Status; note 6 Receive Buffer Status; note 7 SJA1000 VALUE FUNCTION 1 overrun; a message was lost because there was not enough space for that message in the RXFIFO 0 absent; no data overrun has occurred since the last clear data overrun command was given 1 full; one or more complete messages are available in the RXFIFO 0 empty; no message is available Notes 1.
Philips Semiconductors Product specification Stand-alone CAN controller 6.4.6 SJA1000 INTERRUPT REGISTER (IR) The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, a CAN interrupt will be indicated to the CPU. After this register is read by the CPU all bits are reset except for the receive interrupt bit. The interrupt register appears to the CPU as a read only memory.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Notes 1. A wake-up interrupt is also generated, if the CPU tries to set the sleep bit while the CAN controller is involved in bus activities or a CAN interrupt is pending. 2. The behaviour of this bit is equivalent to that of the receive buffer status bit with the exception, that RI depends on the corresponding interrupt enable bit (RIE).
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Note 1. The receive interrupt enable bit has direct influence to the receive interrupt bit and the external interrupt output INT. If RIE is cleared, the external INT pin will become HIGH immediately, if there is no other interrupt pending. 6.4.8 ARBITRATION LOST CAPTURE REGISTER (ALC) This register contains information about the bit position of losing arbitration.
Philips Semiconductors Product specification Stand-alone CAN controller handbook, full pagewidth SJA1000 start of frame arbitration lost TX RX ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 SRTR IDE MGK620 Fig.6 Example of arbitration lost bit number interpretation; result: ALC = 08.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 18 Function of bits 4 to 0 of the arbitration lost capture register BITS(1) ALC.4 ALC.3 ALC.2 ALC.1 ALC.
Philips Semiconductors Product specification Stand-alone CAN controller 6.4.9 SJA1000 ERROR CODE CAPTURE REGISTER (ECC) This register contains information about the type and location of errors on the bus. The error code capture register appears to the CPU as a read only memory. Table 19 Bit interpretation of the error code capture register (ECC); CAN address 12 BIT SYMBOL NAME VALUE FUNCTION ECC.7(1) ERRC1 Error Code 1 − − ECC.6(1) ERRC0 Error Code 0 − − ECC.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 21 Bit interpretation of bits ECC.4 to ECC.0; note 1 BIT ECC.4 BIT ECC.3 BIT ECC.2 BIT ECC.1 BIT ECC.0 FUNCTION 0 0 0 1 1 start of frame 0 0 0 1 0 ID.28 to ID.21 0 0 1 1 0 ID.20 to ID.18 0 0 1 0 0 bit SRTR 0 0 1 0 1 bit IDE 0 0 1 1 1 ID.17 to ID.13 0 1 1 1 1 ID.12 to ID.5 0 1 1 1 0 ID.4 to ID.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 22 Bit interpretation of the error warning limit register (EWLR); CAN address 13 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EWL.7 EWL.6 EWL.5 EWL.4 EWL.3 EWL.2 EWL.1 EWL.0 6.4.11 RX ERROR COUNTER REGISTER (RXERR) The RX error counter register reflects the current value of the receive error counter. After a hardware reset this register is initialized to logic 0.
Philips Semiconductors Product specification Stand-alone CAN controller 6.4.13 SJA1000 TRANSMIT BUFFER The transmit buffer has a length of 13 bytes and is located in the CAN address range from 16 to 28. The global layout of the transmit buffer is shown in Fig.7. One has to distinguish between the Standard Frame Format (SFF) and the Extended Frame Format (EFF) configuration. The transmit buffer allows the definition of one transmit message with up to eight data bytes. 6.4.13.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 25 TX frame information (SFF); CAN address 16 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FF(1) RTR(2) X(3) X(3) DLC.3(4) DLC.2(4) DLC.1(4) DLC.0(4) Notes 1. Frame format. 2. Remote transmission request. 3. Don’t care; recommended to be compatible to receive buffer (0) in case of using the self reception facility (self test). 4. Data length code bit.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 30 TX identifier 2 (EFF); CAN address 18; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID.20 ID.19 ID.18 ID.17 ID.16 ID.15 ID.14 ID.13 Note 1. ID.X means identifier bit X. Table 31 TX identifier 3 (EFF); CAN address 19; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID.12 ID.11 ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 BIT 3 BIT 2 BIT 1 BIT 0 ID.0 X(2) X(3) X(3) Note 1.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 The lower the binary value of the identifier the higher the priority. This is due to the larger number of leading dominant bits during arbitration. 6.4.13.5 6.4.14 RECEIVE BUFFER The global layout of the receive buffer is very similar to the transmit buffer described in the previous section. The receive buffer is the accessible part of the RXFIFO and is located in the range between CAN address 16 and 28.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 35 RX identifier 1 (SFF); CAN address 17; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 Note 1. ID.X means identifier bit X. Table 36 RX identifier 2 (SFF); CAN address 18; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID.20 ID.19 ID.18 RTR(2) 0 0 0 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 DLC.3(3) DLC.2(3) DLC.1(3) DLC.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 41 RX identifier 4 (EFF); can address 20; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID.4 ID.3 ID.2 ID.1 ID.0 RTR(2) 0 0 Notes 1. ID.X means identifier bit X. 2. Remote transmission request. 6.4.15.1 Remark: the received data length code located in the frame information byte represents the real sent data length code, which may be greater than 8 (depends on sender).
Philips Semiconductors Product specification Stand-alone CAN controller MSB handbook, full pagewidth SJA1000 LSB MSB LSB MSB LSB MSB LSB CAN ADDRESS 16; ACR0 CAN ADDRESS 17; ACR1 CAN ADDRESS 18; ACR2 CAN ADDRESS 19; ACR3 7 7 7 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 CAN ADDRESS 20; AMR0 CAN ADDRESS 21; AMR1 CAN ADDRESS 22; AMR2 CAN ADDRESS 23; AMR3 7 7 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DB1.7 DB1.6 DB1.5 DB1.4 DB1.3 DB1.
Philips Semiconductors Product specification Stand-alone CAN controller MSB handbook, full pagewidth SJA1000 LSB MSB LSB MSB CAN ADDRESS 16; ACR0 CAN ADDRESS 17; ACR1 7 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 LSB MSB LSB CAN ADDRESS 18; ACR2 CAN ADDRESS 19; ACR3 7 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 unused CAN ADDRESS 20; AMR0 CAN ADDRESS 21; AMR1 CAN ADDRESS 22; AMR2 CAN ADDRESS 23; AMR3 7 7 7 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 MSB handbook, full pagewidth LSB MSB LSB CAN ADDRESS 16; ACR0 CA 17; ACR1 7 7 6 5 4 3 2 1 0 6 5 4 LSB CA 17; ACR1 CA 19; ACR3 3 3 2 1 0 2 1 0 CA 21; AMR1 CA 21; AMR1 CA 23; AMR3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 0 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 RTR DB1.7 DB1.6 DB1.5 DB1.4 DB1.3 DB1.2 DB1.1 DB1.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Extended frame: if an extended frame message is received, the two defined filters are looking identically. Both filters are comparing the first two bytes of the extended identifier range only. For a successful reception of a message, all single bit comparisons of at least one complete filter have to indicate acceptance.
Philips Semiconductors Product specification Stand-alone CAN controller 6.4.16 SJA1000 RX MESSAGE COUNTER (RMC) The RMC register (CAN address 29) reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. After any reset event, this register is cleared.
Philips Semiconductors Product specification Stand-alone CAN controller 6.5 SJA1000 Common registers BUS TIMING REGISTER 0 (BTR0) 6.5.1 The contents of the bus timing register 0 defines the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW). This register can be accessed (read/write) if the reset mode is active. In operating mode this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected.
Philips Semiconductors Product specification Stand-alone CAN controller 6.5.2.2 SJA1000 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2) TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point, where: tSYNCSEG = 1 × tscl tTSEG1 = tscl × (8 × TSEG1.3 + 4 × TSEG1.2 + 2 × TSEG1.1 + TSEG1.0 + 1) tTSEG2 = tscl × (4 × TSEG2.2 + 2 × TSEG2.1 + TSEG2.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth VDD OCTP1 OCTN1 TP0 OCPOL1 TX0 TN0 OCTP0 OCTN0 OCPOL0 VSS TRANSMIT LOGIC transmitter VDD OCMODE1 OCMODE0 TP1 TX1 TN1 TXCLK TXD VSS MGK629 Fig.14 Transceiver input/output control logic. If the SJA1000 is in the sleep mode a recessive level is output on the TX0 and TX1 pins with respect to the contents within the output control register.
Philips Semiconductors Product specification Stand-alone CAN controller 6.5.3.2 SJA1000 Clock output mode For the TX0 pin this is the same as in normal output mode. However, the data stream to TX1 is replaced by the transmit clock (TXCLK). The rising edge of the transmit clock (non-inverted) marks the beginning of a bit period. The clock pulse width is 1 × tscl. handbook, full pagewidth HIGH TX0 LOW HIGH TX1 LOW MGK630 1 bit time Fig.15 Example of clock output mode. 6.5.3.
Philips Semiconductors Product specification Stand-alone CAN controller handbook, full pagewidth SJA1000 recessive bitstream dominant HIGH TX0 LOW HIGH TX1 LOW MGK631 Fig.16 Bi-phase output mode example (output control register = F8H). 6.5.3.4 Test output mode f osc In test output mode the level connected to RX is reflected at TXn with the next positive edge of the system clock -------2 corresponding to the programmed polarity in the output control register.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Table 48 Output pin configuration; note 1 TXD OCTPX OCTNX OCPOLX TPX(2) TNX(3) TXX(4) Float X 0 0 X off off float Pull-down 0 0 1 0 off on LOW 1 0 1 0 off off float 0 0 1 1 off off float 1 0 1 1 off on LOW 0 1 0 0 off off float 1 1 0 0 on off HIGH 0 1 0 1 on off HIGH 1 1 0 1 off off float 0 1 1 0 off on LOW 1 1 1 0 on off HIGH 0 1 1 1 o
Philips Semiconductors Product specification Stand-alone CAN controller 6.5.4.1 SJA1000 CD.2 to CD.0 The bits CD.2 to CD.0 are accessible without restrictions in reset mode as well as in operating mode. These bits are used to define the frequency at the external CLKOUT pin. For an overview of selectable frequencies see Table 50. Table 50 CLKOUT frequency selection; note 1 CD.2 CD.1 CD.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all voltages referenced to VSS. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage −0.5 +6.
Philips Semiconductors Product specification Stand-alone CAN controller SYMBOL SJA1000 PARAMETER CONDITIONS MIN. MAX. UNIT Inputs VIL1 LOW-level input voltage on pins ALE/AS, CS, RD/E, WR and MODE −0.5 +0.8 V VIL2 LOW-level input voltage on pins XTAL1 and INT − 0.3VDD V VIL3 LOW-level input voltage on pins RST, AD0 to AD7 and RX0(5) −0.5 +0.6 V VIH1 HIGH-level input voltage on pins ALE/AS, CS, RD/E, WR and MODE 2.0 VDD + 0.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 10 AC CHARACTERISTICS VDD = 5 V ±10%; VSS = 0 V; CL = 50 pF (output pins); Tamb = −40 to +125 °C; unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. MAX.
Philips Semiconductors Product specification Stand-alone CAN controller 10.1 SJA1000 AC timing diagrams handbook, full pagewidth A7 to A0 AD7 to AD0 D7 to D0 tRHDZ th(AL-A) tsu(A-AL) ALE (pin ALE/AS) tRLQV tW(AL) tLLRL RD (pin RD/E) tW(R) WR tRHCH tCLRL CS MGK632 Fig.17 Read cycle timing diagram; Intel mode.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 handbook, full pagewidth AD7 to AD0 A7 to A0 D7 to D0 tsu(A-AL) tWHDX th(AL-A) ALE (pin ALE/AS) tW(AL) tWHLH tDVWH tLLWL WR tW(W) RD (pin RD/E) tCLWL tWHCH CS MGK634 Fig.19 Write cycle timing diagram; Intel mode.
Philips Semiconductors Product specification Stand-alone CAN controller 10.2 SJA1000 Additional AC information To provide optimum noise immunity under worst case conditions, the chip is powered by three separate pins and grounded by three separate pins. VDD1 VDD2 handbook, full pagewidth RX0 VDD3 INPUT COMPARATOR TX0 LOGIC RX1 TX1 VSS1 VSS2 VSS3 MGK636 Fig.21 Optimized noise immunity block diagram.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 11 PACKAGE OUTLINES seating plane handbook, full pagewidthdual in-line package; 28 leads (600 mil) DIP28: plastic SOT117-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 15 28 pin 1 index E 1 14 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4.0 1.7 1.3 0.53 0.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 14 1 e w M bp 0 detail X 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. 12 SOLDERING 12.1 Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). 12.3.
Philips Semiconductors Product specification Stand-alone CAN controller 12.
Philips Semiconductors Product specification Stand-alone CAN controller SJA1000 NOTES 2000 Jan 04 67
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