Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsSLRC40001T/OFE,112

1. Introduction

This data sheet describes the functionality of the SLRC400 Integrated Circuit (IC). It

includes the functional and electrical specifications and from a system and hardware

viewpoint gives detailed information on how to design-in the device.

2. General description

The SLRC400 is a member of a new family of highly integrated reader ICs for contactless

communication at 13.56 MHz. This family of reader ICs provide:

• outstanding modulation and demodulation for passive contactless communication

• a wide range of methods and protocols

The transmitter module Section 8.9 on page 24

can directly drive an antenna designed for

proximity operating distance up to 100 mm without additional active circuitry. The receiver

module provides a robust and efficient demodulation/decoding circuitry implementation for

compatible transponder signals (see Section 8.10 on page 28

All layers of the ICODE1 and ISO/IEC 15693 protocols are supported. The receiver

module provides a robust and efficient demodulation/decoding circuitry implementation for

ICODE1 and ISO/IEC 15693 compatible transponder signals. The digital module

manages ICODE1 and ISO/IEC 15693 framing and error detection (CRC).

A parallel interface can be directly connected to any 8-bit microprocessor to ensure

reader/terminal design flexibility.

3. Features and benefits

3.1 General

 Highly integrated analog circuitry for demodulating and decoding label response

 Buffered output drivers enable antenna connection using the minimum of external

components

 Proximity operating distance up to 100 mm

 Supports both ICODE1 and ISO/IEC 15693 protocols

 Parallel microprocessor interface with internal address latch and IRQ line

 Flexible interrupt handling

 Automatic detection of parallel microprocessor interface type

 64-byte send and receive FIFO buffer

 Hard reset with low power function

SLRC400

ICODE reader IC

Rev. 3.3 — 23 March 2010

054333

Product data sheet

PUBLIC

Summary of content (101 pages)

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SLRC400 ICODE reader IC Rev. 3.3 — 23 March 2010 054333 Product data sheet PUBLIC 1. Introduction This data sheet describes the functionality of the SLRC400 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. 2. General description The SLRC400 is a member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz.
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SLRC400 NXP Semiconductors ICODE reader IC Software controlled Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz connection Clock frequency filtering 3.3 V operation for transmitter (antenna driver) in short range and proximity applications 4.
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SLRC400 NXP Semiconductors ICODE reader IC 6.
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SLRC400 NXP Semiconductors ICODE reader IC 7. Pinning information OSCIN 1 32 OSCOUT IRQ 2 31 RSTPD n.c. 3 30 VMID SIGOUT 4 29 RX TX1 5 28 AVSS TVDD 6 27 AUX TX2 7 26 AVDD TVSS 8 NCS 9 SLRC400 25 DVDD 24 A2 23 A1 NWR/R/NW/nWrite 10 22 A0/nWait NRD/NDS/nDStrb 11 21 ALE/AS/nAStrb DVSS 12 AD0/D0 13 20 D7/AD7 AD1/D1 14 19 D6/AD6 AD2/D2 15 18 D5/AD5 17 D4/AD4 AD3/D3 16 001aal581 Fig 2. SLRC400 pin configuration 7.1 Pin description Table 2.
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SLRC400 NXP Semiconductors ICODE reader IC Table 2.
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SLRC400 NXP Semiconductors ICODE reader IC 8. Functional description 8.1 Digital interface 8.1.1 Overview of supported microprocessor interfaces The SLRC400 supports direct interfacing to various 8-bit microprocessors. Alternatively, the SLRC400 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 3 shows the parallel interface signals supported by the SLRC400. Table 3.
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SLRC400 NXP Semiconductors ICODE reader IC 8.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 4. Table 4. SLRC400 pins 8.1.3.
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SLRC400 NXP Semiconductors ICODE reader IC 8.1.3.2 Common read and write strobe address bus (A3 to An) ADDRESS DECODER DEVICE NCS non-multiplexed address ADDRESS DECODER LOW A2 HIGH address bus (A0 to A2) A1 LOW A0 to A2 data bus (D0 to D7) A0 multiplexed address/data (AD0 to AD7) AD0 to AD7 D0 to D7 HIGH Address strobe (AS) ALE Data strobe (NDS) Read/Write (R/NW) DEVICE NCS ALE Data strobe (NDS) NRD NRD Read/Write (R/NW) NWR NWR 001aak608 Fig 4.
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SLRC400 NXP Semiconductors ICODE reader IC 8.2 Memory organization of the EEPROM Table 5. EEPROM memory organization diagram Block Position Address Byte address Access Memory content Refer to 0 0 00h to 0Fh R product information field Section 8.2.1 on page 9 1 1 10h to 1Fh R/W Section 8.2.2.1 on page 10 2 2 20h to 2Fh R/W StartUp register initialization file 3 3 30h to 3Fh R/W 4 4 40h to 4Fh R/W register initialization file 5 5 50h to 5Fh R/W Section 8.2.2.
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SLRC400 NXP Semiconductors ICODE reader IC Table 8. Product type identification definition Definition Product type identification bytes Byte 0 1 2 3 4[1] Value 30h 33h F1h 00h XXh [1] Byte 4 contains the current version number. 8.2.2 Register initialization file (read/write) Register initialization from address 10h to address 2Fh is performed automatically during the initializing phase (see Section 8.7.3 on page 23) using the StartUp register initialization file.
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SLRC400 NXP Semiconductors ICODE reader IC Table 10.
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SLRC400 NXP Semiconductors ICODE reader IC 8.2.2.3 Register initialization file (read/write) The EEPROM memory content from block address 3 to 7 can initialize register sub addresses 10h to 2Fh when the LoadConfig command is executed (see Section 10.4.1 on page 75). This command requires the EEPROM starting byte address as a two byte argument for the initialization procedure. The byte assignment is shown in Table 11. Table 11.
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SLRC400 NXP Semiconductors ICODE reader IC Table 12. FIFO buffer access …continued Active command FIFO buffer μP Write μP Read Remark Transceive yes yes WriteE2 yes - ReadE2 yes yes LoadConfig yes - CalcCRC yes - the microprocessor has to know the state of the command (transmitting or receiving) the microprocessor has to prepare the arguments, afterwards only reading is allowed 8.3.
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SLRC400 NXP Semiconductors ICODE reader IC Table 13. Associated FIFO buffer registers and flags Flags Register name Bit Register address FIFOLength[6:0] FIFOLength 6 to 0 04h FIFOOvfl ErrorFlag 4 0Ah FlushFIFO Control 0 09h HiAlert PrimaryStatus 1 03h HiAlertIEn InterruptEn 1 06h HiAlertIRq InterruptRq 1 07h LoAlert PrimaryStatus 0 03h LoAlertIEn InterruptEn 0 06h LoAlertIRq InterruptRq 0 07h WaterLevel[5:0] FIFOLevel 5 to 0 29h 8.
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SLRC400 NXP Semiconductors ICODE reader IC Table 14.
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SLRC400 NXP Semiconductors ICODE reader IC • bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When it is set to logic 0, it is an open-drain output which requires an external resistor to achieve a HIGH-level at pin IRQ. Remark: During the reset phase (see Section 8.7.2 on page 23) bit IRQInv is set to logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ. 8.4.
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SLRC400 NXP Semiconductors ICODE reader IC 8.5.1 Timer unit implementation 8.5.1.1 Timer unit block diagram Figure 6 shows the block diagram of the timer module. TStartTxBegin TReloadValue[7:0] TxBegin Event TStartTxEnd PARALLEL IN TxEnd Event START COUNTER/ PARALLEL LOAD TAutoRestart TStartNow Q S COUNTER MODULE (x ≤ x − 1) Q TRunning R TStopNow STOP COUNTER RxEnd Event TStopRxEnd RxBegin Event TStopRxBegin TPreScaler[4:0] 13.
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SLRC400 NXP Semiconductors ICODE reader IC The timer is started immediately by loading a value from the TimerReload register into the counter module.
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SLRC400 NXP Semiconductors ICODE reader IC 8.5.1.4 Timer unit status The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start events start the timer at the TReloadValue[7:0] and changes the status flag TRunning to logic 1. Conversely, configured stop events stop the timer and sets the TRunning status flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register changes on the next timer unit clock cycle.
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SLRC400 NXP Semiconductors ICODE reader IC Table 17. TimeSlotPeriod ICODE1 mode TimeSlotPeriod for TSP1 TimeSlotPeriod for TSP2 standard mode BFh 1BFh fast mode 5Fh 67h Remark: Set bit TxCRCEn to logic 0 before the Quit frame is sent. If TxCRCEn is not set to logic 0, the Quit frame is sent with a calculated CRC value. Use the CRC8 algorithm to calculate the Quit value. 8.5.2 Using the timer unit functions 8.5.2.
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SLRC400 NXP Semiconductors ICODE reader IC Table 18. Associated timer unit registers and flags …continued Flags Register name Bit Register address TStartTxBegin TimerControl 0 2Bh TStartTxEnd TimerControl 1 2Bh TStopNow Control 2 09h TStopRxBegin TimerControl 2 2Bh TStopRxEnd TimerControl 3 2Bh 8.6 Power reduction modes 8.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator.
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SLRC400 NXP Semiconductors ICODE reader IC After resetting the Control register bit PowerDown, the bit indicating Soft power-down mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The PowerDown bit is automatically cleared when the Soft power-down mode is exited. Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable.
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SLRC400 NXP Semiconductors ICODE reader IC 8.7.2 Reset phase The reset phase automatically follows the Hard power-down. Once the oscillator is running stably, the reset phase takes 512 clock cycles. During the reset phase, some register bits are preset by hardware. The respective reset values are given in the description of each register (see Section 9.5 on page 40). Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable.
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SLRC400 NXP Semiconductors ICODE reader IC 8.8 Oscillator circuit DEVICE OSCOUT OSCIN 13.56 MHz 15 pF 15 pF 001aak614 Fig 9. Quartz clock connection The clock applied to the SLRC400 acts as a time basis for the synchronous system encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain highest performance, clock jitter must be as small as possible.
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SLRC400 NXP Semiconductors ICODE reader IC Table 21. Pin TX2 configurations TxControl register configuration TX2RFEn TX2Cw Envelope TX2 signal TX2Inv 0 X X X LOW (GND) 1 0 0 0 13.56 MHz modulated carrier 1 0 0 1 13.56 MHz unmodulated carrier 1 0 1 0 13.56 MHz modulated carrier frequency, 180° phase-shift relative to TX1 1 0 1 1 13.56 MHz unmodulated carrier, 180° phase-shift relative to TX1 1 1 0 X 13.56 MHz unmodulated carrier 1 1 1 X 13.
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SLRC400 NXP Semiconductors ICODE reader IC 8.9.3.1 Source resistance table Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW MANT = Mantissa; EXP = Exponent. GsCfgCW (decimal) EXPGsCfgCW (decimal) MANTGsCfgCW (decimal) RS(ref) (Ω) GsCfgCW (decimal) EXPGsCfgCW (decimal) MANTGsCfgCW (decimal) RS(ref) (Ω) 0 0 0 ∝ 24 1 8 0.0652 16 1 0 ∝ 25 1 9 0.0580 32 2 0 ∝ 37 2 5 0.0541 48 3 0 ∝ 26 1 10 0.0522 1 0 1 1.0000 27 1 11 0.
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SLRC400 NXP Semiconductors ICODE reader IC Table 23. Modulation index values GsCfgMod[5:0] (Hex) Relative resistance during modulation (Ω) Modulation index (Rant = 50 Ω) (%) GsCfgMod[5:0] (Hex) Relative resistance during modulation (Ω) Modulation index (Rant = 50 Ω) (%) 00 ∝ - 18 0.065 4.15 10 ∝ - 19 0.058 3.63 20 ∝ - 25 0.054 3.35 30 ∝ - 1A 0.052 3.22 01 1 43.45 1B 0.047 2.87 11 0.522 28.44 33 0.047 2.82 02 0.5 27.57 26 0.045 2.69 03 0.333 20.
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SLRC400 NXP Semiconductors ICODE reader IC 8.9.3.3 Calculating the relative source resistance The reference source resistance RS(ref) can be calculated using Equation 6. 1 R S ( ref ) = ------------------------------------------------------------------------------EXP GsCfgCW 77 MANT GsCfgCW • ⎛ ------⎞ ⎝ 40⎠ 8.9.3.
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SLRC400 NXP Semiconductors ICODE reader IC The demodulated signal is amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the expected and the received signal. The BitPhase register enables correlation interval position alignment with the received signal’s bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
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SLRC400 NXP Semiconductors ICODE reader IC calibration impulse from reset sequence a rising edge initiates Q-clock calibration calibration impulse from end of Transceive command ClkQCalib bit 001aak616 Fig 11. Automatic Q-clock calibration Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or approximately 4.8 μs. The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift between the Q-clock and the I-clock.
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SLRC400 NXP Semiconductors ICODE reader IC The correlation circuitry needs the phase information for the incoming label signal for optimum performance. This information is defined for the microprocessor using the BitPhase register. This value defines the phase relationship between the transmitter and receiver clock in multiples of the BitPhase time (tBitPhase) = 1 / 13.56 MHz. 8.10.2.
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SLRC400 NXP Semiconductors ICODE reader IC serial data out MILLER CODER 1 OUT OF 256 RZ OR 1 OUT OF 4 0 0 1 1 envelope 2 reserved 3 TX1 MODULATOR TX2 2 (part of) serial data processing envelope transmit NRZ Manchester with subcarrier Manchester reserved reserved 3 4 5 6 7 reserved 2 3 Manchester out 0 reserved 1 internal 2 1 MANCHESTER DECODER 0 1 0 serial data in (part of) analog circuitry Modulator Source[1:0] 0 DRIVER 2 Decoder Source[1:0] 3 SERIAL SIGNAL
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SLRC400 NXP Semiconductors ICODE reader IC Table 26. ModulatorSource[1:0] values See Table 86 on page 54 for additional information. Number ModulatorSource Input signal to modulator [1:0] 0 00 constant 0 (carrier signal off on pins TX1 and TX2) 1 01 constant 1 (continuous carrier signal on pins TX1 and TX2) 2 10 modulation signal (envelope) from the internal encoder. This is the default configuration.
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SLRC400 NXP Semiconductors ICODE reader IC 9. SLRC400 registers 9.1 Register addressing modes Three methods can be used to operate the SLRC400: • initiating functions and controlling data by executing commands • configuring the functional operation using a set of configuration bits • monitoring the state of the SLRC400 by reading status flags The commands, configuration bits and flags are accessed using the microprocessor interface.
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SLRC400 NXP Semiconductors ICODE reader IC Table 30. Behavior and designation of register bits Abbreviation Behavior Description R/W read and write These bits can be read and written by the microprocessor. Since they are only used for control, their content is not influenced by internal state machines. Example: TimerReload register may be read and written by the microprocessor. It will also be read by internal state machines but never changed by them.
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SLRC400 NXP Semiconductors ICODE reader IC 9.3 Register overview Table 31.
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SLRC400 NXP Semiconductors ICODE reader IC Table 31.
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SLRC400 NXP Semiconductors ICODE reader IC 9.4 SLRC400 register flags overview Table 32.
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SLRC400 NXP Semiconductors ICODE reader IC Table 32.
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SLRC400 NXP Semiconductors ICODE reader IC Table 32. SLRC400 register flags overview …continued Flag(s) Register Bit Address TxIEn InterruptEn 4 06h TxIRq InterruptRq 4 07h TxLastBits[2:0] BitFraming 2 to 0 0Fh UsePageSelect Page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h WaterLevel[5:0] FIFOLevel 5 to 0 29h ZeroAfterColl DecoderControl 5 1Ah 9.5 Register descriptions 9.5.1 Page 0: Command and status 9.5.1.1 Page register Selects the page register. Table 33.
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SLRC400 NXP Semiconductors ICODE reader IC Table 36. 9.5.1.3 Command register bit descriptions Bit Symbol Value Description 7 IFDetectBusy - shows the status of interface detection logic 0 interface detection finished successfully 1 interface detection ongoing 6 0 - reserved 5 to 0 Command[5:0] - activates a command based on the Command code. Reading this register shows which command is being executed. FIFOData register Input and output of the 64 byte FIFO buffer. Table 37.
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SLRC400 NXP Semiconductors ICODE reader IC Table 40.
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SLRC400 NXP Semiconductors ICODE reader IC Table 42. FIFOLength bit descriptions Bit Symbol Description 7 0 reserved 6 to 0 FIFOLength[6:0] 9.5.1.6 gives the number of bytes stored in the FIFO buffer. Writing increments the FIFOLength register value while reading decrements the FIFOLength register value SecondaryStatus register Various secondary status flags. Table 43.
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SLRC400 NXP Semiconductors ICODE reader IC Table 46. Bit Symbol Value Description 2 IdleIEn - sends the IdleIRq idle interrupt request to pin IRQ[1] 1 HiAlertIEn - sends the HiAlertIRq high alert interrupt request to pin IRQ[1] 0 LoAlertIEn - sends the LoAlertIRq low alert interrupt request to pin IRQ[1] [1] 9.5.1.8 InterruptEn register bit descriptions …continued This bit can only be set or cleared using bit SetIEn. InterruptRq register Interrupt request flags. Table 47.
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SLRC400 NXP Semiconductors ICODE reader IC 9.5.2 Page 1: Control and status 9.5.2.1 Page register Selects the page register; see Section 9.5.1.1 “Page register” on page 40. 9.5.2.2 Control register Various control flags, for timer, power saving, etc. Table 49. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation Bit 7 5 4 3 2 1 0 Symbol 00 StandBy PowerDown 0 TStopNow TStartNow FlushFIFO Access R/W D D D W W W Table 50. Bit 9.5.2.
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SLRC400 NXP Semiconductors ICODE reader IC Table 52. 9.5.2.4 ErrorFlag register bit descriptions …continued Bit Symbol Value Description 2 FramingErr 1 set when the SOF is incorrect 0 automatically set during the PrepareRx state in the receiver start phase 1 0 - reserved 0 CollErr 1 set when a bit-collision is detected 0 automatically set during the PrepareRx state in the receiver start phase CollPos register Bit position of the first bit-collision detected on the RF interface.
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SLRC400 NXP Semiconductors ICODE reader IC Table 57. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 5 4 3 2 Symbol CRCResultLSB[7:0] Access R Table 58. 9.5.2.7 6 1 0 CRCResultLSB register bit descriptions Bit Symbol Description 7 to 0 CRCResultLSB[7:0] gives the CRC register’s least significant byte value; only valid if CRCReady = logic 1 CRCResultMSB register MSB of the CRC coprocessor register. Table 59.
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SLRC400 NXP Semiconductors ICODE reader IC Table 62. BitFraming register bit descriptions Bit Symbol Value Description 7 0 - reserved 6 to 4 RxAlign[2:0] defines the bit position for the first bit received to be stored in the FIFO buffer. Additional received bits are stored in the next subsequent bit positions. After reception, RxAlign[2:0] is automatically cleared.
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SLRC400 NXP Semiconductors ICODE reader IC Table 64. Bit Symbol Value Description 2 TX2Cw 1 the output on pin TX2 is a continuously unmodulated 13.56 MHz carrier 0 enables modulation of the 13.56 MHz carrier signal 1 the output signal on pin TX2 is the 13.56 MHz carrier modulated by the transmission data 0 TX2 is driven at a constant output level 1 the output signal on pin TX1 is the 13.56 MHz carrier modulated by the transmission data 0 TX1 is driven at a constant output level 1 0 9.
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SLRC400 NXP Semiconductors ICODE reader IC 9.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 69. CoderControl register (address: 14h) reset value: 0010 1100b, 2Ch bit allocation Bit 7 6 Symbol SendOnePulse 0 CoderRate[2:0] TxCoding[2:0] Access R/W R/W R/W R/W Table 70. 3 2 1 0 Bit Symbol Value Description 7 SendOnePulse 1 forces ISO/IEC 15693 modulation. Used to switch to the next TimeSlotPeriod if the Inventory command is used.
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SLRC400 NXP Semiconductors ICODE reader IC 9.5.3.6 ModWidth register Selects the pulse-modulation width. Table 71. ModWidth register (address: 15h) reset value: 0011 1111b, 3Fh bit allocation Bit 9.5.3.7 7 6 4 3 2 Symbol ModWidth[7:0] Access R/W 1 0 Table 72. ModWidth register bit descriptions Bit Symbol Description 7 to 0 ModWidth[7:0] defines the width of the modulation pulse based on tmod = 2 × (ModWidth + 1) / fclk where fclk = 13.56 MHz oscillator clock.
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SLRC400 NXP Semiconductors ICODE reader IC Table 76. RxControl1 register (address: 19h) reset value: 1000 1011b, 8Bh bit allocation Bit 7 6 5 3 2 1 0 Symbol SubCPulses[2:0] 0 1 0 Gain[1:0] Access R/W R/W R/W R/W R/W Table 77.
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SLRC400 NXP Semiconductors ICODE reader IC Table 79. Bit DecoderControl register bit descriptions …continued Symbol Value Description 4 to 3 RxFraming[1:0] 2 selects the received frame type RxInvert 1 to 0 00 9.5.4.
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SLRC400 NXP Semiconductors ICODE reader IC Table 84. BPSKDemControl register (address: 1Dh) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 Symbol 0 0 0 Access 9.5.4.7 4 3 2 1 0 0 0 0 0 0 R/W RxControl2 register Controls decoder operation and defines the input source for the receiver. Table 85.
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SLRC400 NXP Semiconductors ICODE reader IC Table 88. ClockQControl register bit descriptions …continued Bit Symbol Value Description 6 ClkQCalib 0 Q-clock is automatically calibrated after the reset phase and after data reception from the label 1 no calibration is performed automatically 5 0 - this value must not be changed 4 to 0 ClkQDelay[4:0] - this register shows the number of delay elements used to generate a 90° phase-shift of the I-clock to obtain the Q-clock.
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SLRC400 NXP Semiconductors ICODE reader IC Table 92. Bit Symbol Value Function 5 CRC3309 1 CRC calculation is performed using ISO/IEC 3309 as defined by ISO/IEC 15693[1] 0 CRC calculation is performed using ICODE1 1 an 8-bit CRC is calculated 0 a 16-bit CRC is calculated 1 the last byte(s) of a received frame are interpreted as CRC bytes. If the CRC is correct, the CRC bytes are not passed to the FIFO. If the CRC bytes are incorrect, the CRCErr flag is set.
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SLRC400 NXP Semiconductors ICODE reader IC Table 96. Bit CRCPresetMSB bit descriptions [1] Symbol Description 7 to 0 CRCPresetMSB[7:0] defines the starting value for CRC calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC command (if the CRC calculation is enabled) Remark: The preset value is the same for both ICODE1 and ISO/IEC 15693. [1] 9.5.5.6 This register is not relevant if CRC8 is set to logic 1.
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SLRC400 NXP Semiconductors ICODE reader IC Table 100. SIGOUTSelect register bit descriptions …continued 9.5.5.
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SLRC400 NXP Semiconductors ICODE reader IC Table 104. TimerClock register (address: 2Ah) reset value: 0000 1011b, 0Bh bit allocation Bit 7 6 5 4 3 2 1 Symbol 00 TAutoRestart TPreScaler[4:0] Access R/W RW RW 0 Table 105.
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SLRC400 NXP Semiconductors ICODE reader IC Table 108. TimerReload register (address: 2Ch) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 Symbol TReloadValue[7:0] Access R/W 2 1 0 Table 109. TimerReload register bit descriptions Bit Symbol Description 7 to 0 TReloadValue[7:0] 9.5.6.6 on a start event, the timer loads the TReloadValue[7:0] value. Changing this register only affects the timer on the next start event. If TReloadValue[7:0] is set to logic 0 the timer cannot start.
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SLRC400 NXP Semiconductors ICODE reader IC 9.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h These registers are reserved for future use. Table 114. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W 9.5.8 Page 7: Test control 9.5.8.1 Page register Selects the page register; see Section 9.5.1.1 “Page register” on page 40. 9.
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SLRC400 NXP Semiconductors ICODE reader IC Table 117. TestAnaSelect bit descriptions 9.5.8.4 Bit Symbol Value Description 7 to 4 0000 - these values must not be changed 3 to 0 TestAnaOutSel[4:0] selects the internal analog signal to be routed to pin AUX. See Section 14.2.2 on page 88 for detailed information.
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SLRC400 NXP Semiconductors ICODE reader IC Table 121. TestDigiSelect register bit descriptions Bit Symbol Value Description 7 SignalToSIGOUT 1 overrules the SIGOUTSelect[2:0] setting and routes the digital test signal defined with the TestDigiSignalSel[6:0] bits to pin SIGOUT 0 SIGOUTSelect[2:0] defines the signal on pin SIGOUT - selects the digital test signal to be routed to pin SIGOUT. Refer to Section 14.2.3 on page 88 for detailed information.
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SLRC400 NXP Semiconductors ICODE reader IC 10. SLRC400 command set SLRC400 operation is determined by an internal state machine capable of performing a command set. The commands can be started by writing the command code to the Command register. Arguments and/or data necessary to process a command are mainly exchanged using the FIFO buffer.
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SLRC400 NXP Semiconductors ICODE reader IC Table 123. SLRC400 commands overview …continued Command ReadE2 Value 03h Action FIFO communication reads data from the EEPROM and sends it to the FIFO buffer. See Section 10.3.2 on page 75. Remark: Keys cannot be read back Arguments and data sent Data received start address LSB data bytes start address MSB number of data bytes LoadConfig 07h reads data from EEPROM and initializes the SLRC400 registers. See Section 10.4.1 on page 75.
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SLRC400 NXP Semiconductors ICODE reader IC 10.1.3 Idle command 00h Table 125. Idle command 00h Command Value Action Arguments and data Returned data Idle 00h no action; cancels current command execution - - The Idle command switches the SLRC400 to its inactive state where it waits for the next command. It does not need or return, any data. The device automatically enters the idle state when a command finishes. When this happens, the SLRC400 sends an interrupt request by setting bit IdleIRq.
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SLRC400 NXP Semiconductors ICODE reader IC 3. Part of the data transmitted to the label is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. While the Transmit command is active, the microprocessor can send further data to the FIFO buffer. This is then appended by the transmitter to the transmitted data stream.
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SLRC400 NXP Semiconductors ICODE reader IC TxLastBits[2:0] TxLastBits = 0 FIFOLength[6:0] 0x01 0x00 FIFO empty TxData 7 0 7 0 7 check FIFO empty accept further data 001aak619 Fig 13. Timing for transmitting byte oriented frames As long as the internal accept further data signal is logic 1, further data can be written to the FIFO buffer. The SLRC400 appends this data to the data stream transmitted using the RF interface.
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SLRC400 NXP Semiconductors ICODE reader IC 10.2.2.2 RF channel redundancy and framing The ISO/IEC 15693 decoder expects the SOF pattern at the beginning of each data stream. When the SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. The ICODE1 decoder however, does not expect an SOF pattern at the start of each data stream, but activates the serial-to-parallel converter when the first data bit is received.
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SLRC400 NXP Semiconductors ICODE reader IC Table 128. Return values for bit-collision positions Collision in bit CollPos register value (Decimal) SOF 0 Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1 … … Most Significant Bit (MSB) of the LSByte 8 LSB of second byte 9 … … MSB of second byte 16 LSB of third byte 17 … … If a collision is detected in the SOF, a frame error is flagged and no data is sent to the FIFO buffer.
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SLRC400 NXP Semiconductors ICODE reader IC 10.2.4 States of the label communication The status of the transmitter and receiver state machine can be read from bits ModemState[2:0] in the PrimaryStatus register. The assignment of ModemState[2:0] to the internal action is shown in Table 131. Table 131.
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SLRC400 NXP Semiconductors ICODE reader IC 10.2.
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SLRC400 NXP Semiconductors ICODE reader IC 10.3 EEPROM commands 10.3.1 WriteE2 command 01h Table 132. WriteE2 command 01h Command Value Action FIFO Arguments and data WriteE2 01h get data from FIFO buffer and write it to the EEPROM Returned data start address LSB - start address MSB - data byte stream - The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address.
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SLRC400 NXP Semiconductors ICODE reader IC 10.3.1.2 Timing diagram Figure 15 shows programming five bytes into the EEPROM. tprog,del NWR data write E2 addr LSB addr byte 0 MSB byte 1 byte 2 byte 3 Idle command byte 4 WriteE2 command active EEPROM programming tprog tprog tprog programming byte 0 programming byte 1, byte 2 and byte 3 programming byte 4 E2Ready TxIRq 001aak623 Fig 15.
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SLRC400 NXP Semiconductors ICODE reader IC 10.3.2 ReadE2 command 03h Table 133. ReadE2 command 03h Command Value Action Arguments Returned data ReadE2 03h start address LSB data bytes reads EEPROM data and stores it in the FIFO buffer start address MSB number of data bytes The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned.
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SLRC400 NXP Semiconductors ICODE reader IC 10.4.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. 10.4.2 CalcCRC command 12h Table 135. CalcCRC command 12h Command Value Action Arguments and data Returned data CalcCRC data byte stream - 12h activates the CRC coprocessor The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the CRC coprocessor.
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SLRC400 NXP Semiconductors ICODE reader IC When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC validity for the processed data. 10.5 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set.
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SLRC400 NXP Semiconductors ICODE reader IC 12.2 Current consumption Table 140.
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SLRC400 NXP Semiconductors ICODE reader IC Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by a RC low-pass filter which causes a propagation delay on the reset signal. Table 143. RSTPD input pin characteristics Symbol Parameter ILI input leakage current Vth threshold voltage tPD Conditions Min Typ Max Unit −1.0 - +1.0 μA positive-going threshold; CMOS = VDDD < 3.6 V 0.65VDDD - 0.75VDDD V negative-going threshold; CMOS = VDDD < 3.6 V 0.
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SLRC400 NXP Semiconductors ICODE reader IC Table 146. Antenna driver output pin characteristics Symbol Parameter Conditions VOH HIGH-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA VOL LOW-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA VDD(TVDD) = 5.0 V; IOL = 100 mA IO output current Min Typ Max Unit - 4.97 - V - 4.85 - V - 30 - mV VDD(TVDD) = 5.0 V; IOL = 100 mA - 150 - mV transmitter; continuous wave; peak-to-peak - - 200 mA 12.
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SLRC400 NXP Semiconductors ICODE reader IC tLHLL ALE tSLRWL tRWHSH NCS tLLRWL tRWHRWL tRWLRWH tRWHRWL NWR NRD tAVLL D0 to D7 tWLQV tRLDV tLLAX A0 to A2 tWHDX tRHDZ D0 to D7 Multiplexed address bus tAVRWL A0 to A2 tWHAX A0 to A2 Separated address bus 001aaj638 Fig 16. Separate read/write strobe timing diagram Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care.
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SLRC400 NXP Semiconductors ICODE reader IC Table 148.
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SLRC400 NXP Semiconductors ICODE reader IC Table 149.
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SLRC400 NXP Semiconductors ICODE reader IC 12.4.4 Clock frequency The clock input is pin OSCIN. Table 150. Clock frequency Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency checked by the clock filter - 13.56 - MHz δclk clock duty cycle 40 50 60 % tjit jitter time of clock edges - - 10 ps The clock applied to the SLRC400 acts as a time constant for the synchronous system’s encoder and decoder.
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SLRC400 NXP Semiconductors ICODE reader IC 14. Application information 14.1 Typical application 14.1.1 Circuit diagram Figure 19 shows a typical application where the antenna is directly matched to the SLRC400: DVDD Reset AVDD TVDD DVDD RSTPD AVDD TVDD control lines C1 L0 data bus TX1 MICROPROCESSOR BUS C0 C2a TVSS MICROPROCESSOR C0 L0 IRQ C1 C2b TX2 DEVICE IRQ C3 R1 RX R2 VMID DVSS OSCIN OSCOUT AVSS 13.56 MHz C4 100 nF 15 pF 15 pF 001aak625 Fig 19.
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SLRC400 NXP Semiconductors ICODE reader IC Remark: To achieve best performance, all components must be at least equal in quality to those recommended. Remark: The layout has a major influence on the overall performance of the filter. 14.1.2.2 Antenna matching Due to the impedance transformation of the low-pass filter, the antenna coil has to be matched to a given impedance. The matching elements C1 and C2 can be estimated and have to be fine tuned depending on the design of the antenna coil.
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SLRC400 NXP Semiconductors ICODE reader IC • K = antenna shape factor (K = 1.07 for circular antennas and K = 1.47 for square antennas) • N1 = number of turns • ln = natural logarithm function The values of the antenna inductance, resistance, and capacitance at 13.
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SLRC400 NXP Semiconductors ICODE reader IC 14.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. Table 153.
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SLRC400 NXP Semiconductors ICODE reader IC Table 154. Digital test signal selection …continued TestDigiSignalSel [6:0] Signal name Description C5h wr_sync internal synchronized write signal which is derived from the parallel microprocessor interface 96h int_clock internal 13.56 MHz clock 00h no test signal output as defined by the SIGOUTSelect register SIGOUTSelect[2:0] bits routed to pin SIGOUT If test signals are not used, the TestDigiSelect register address value must be 00h.
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SLRC400 NXP Semiconductors ICODE reader IC receiving path Q-Clock VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data 50 μs per division s_valid 500 μs per division 001aak629 Fig 20. Q-clock receiving path SLRC400_33 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 © NXP B.V. 2010. All rights reserved.
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SLRC400 NXP Semiconductors ICODE reader IC 15. Package outline SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.
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SLRC400 NXP Semiconductors ICODE reader IC 16. Abbreviations Table 155.
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SLRC400 NXP Semiconductors ICODE reader IC 18. Revision history Table 156.
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SLRC400 NXP Semiconductors ICODE reader IC 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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SLRC400 NXP Semiconductors ICODE reader IC In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully
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SLRC400 NXP Semiconductors ICODE reader IC 21. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Ordering information . . . . . . . . . . . . . . . .
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SLRC400 NXP Semiconductors ICODE reader IC Table 79. DecoderControl register bit descriptions . . . . .52 Table 80. BitPhase register (address: 1Bh) reset value: 0101 0100b, 54h bit allocation . . . . . . .53 Table 81. BitPhase register bit descriptions . . . . . . . . . .53 Table 82. RxThreshold register (address: 1Ch) reset value: 0110 1000b, 68h bit allocation . . . . . . .53 Table 83. RxThreshold register bit descriptions . . . . . . .53 Table 84.
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SLRC400 NXP Semiconductors ICODE reader IC Table 151. EEPROM characteristics . . . . . . . . . . . . . . . .84 Table 152. Signal routed to pin SIGOUT . . . . . . . . . . . . .87 Table 153. Analog test signal selection . . . . . . . . . . . . . .88 Table 154. Digital test signal selection . . . . . . . . . . . . . . . 88 Table 155. Abbreviations and acronyms . . . . . . . . . . . . . 92 Table 156. Revision history . . . . . . . . . . . . . . . . . . . . . . . 93 22. Figures Fig 1. Fig 2. Fig 3. Fig 4.
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SLRC400 NXP Semiconductors ICODE reader IC 23. Contents 1 2 3 3.1 4 5 6 7 7.1 8 8.1 8.1.1 8.1.2 8.1.3 8.1.3.1 8.1.3.2 8.1.3.3 8.2 8.2.1 8.2.2 8.2.2.1 8.2.2.2 8.2.2.3 8.3 8.3.1 8.3.1.1 8.3.2 8.3.3 8.3.4 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.3 8.4.4 8.5 8.5.1 8.5.1.1 8.5.1.2 8.5.1.3 8.5.1.4 8.5.1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . .
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SLRC400 NXP Semiconductors ICODE reader IC 9.5.1.2 9.5.1.3 9.5.1.4 9.5.1.5 9.5.1.6 9.5.1.7 9.5.1.8 9.5.2 9.5.2.1 9.5.2.2 9.5.2.3 9.5.2.4 9.5.2.5 9.5.2.6 9.5.2.7 9.5.2.8 9.5.3 9.5.3.1 9.5.3.2 9.5.3.3 9.5.3.4 9.5.3.5 9.5.3.6 9.5.3.7 9.5.3.8 9.5.4 9.5.4.1 9.5.4.2 9.5.4.3 9.5.4.4 9.5.4.5 9.5.4.6 9.5.4.7 9.5.4.8 9.5.5 9.5.5.1 9.5.5.2 9.5.5.3 9.5.5.4 9.5.5.5 9.5.5.6 9.5.5.7 9.5.5.8 9.5.6 9.5.6.1 9.5.6.2 9.5.6.3 9.5.6.4 9.5.6.5 9.5.6.6 9.5.6.7 Command register . . . . . . . . . . . . . . . . . . . . .
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SLRC400 NXP Semiconductors ICODE reader IC 12.3 Pin characteristics . . . . . . . . . . . . . . . . . . . . . 12.3.1 Input pin characteristics . . . . . . . . . . . . . . . . . 12.3.2 Digital output pin characteristics . . . . . . . . . . . 12.3.3 Antenna driver output pin characteristics . . . . 12.4 AC electrical characteristics . . . . . . . . . . . . . . 12.4.1 Separate read/write strobe bus timing . . . . . . 12.4.2 Common read/write strobe bus timing . . . . . . 12.4.3 EPP bus timing . . . . . . .