Datasheet

MPC5674F Microcontroller Data Sheet, Rev. 9
Revision History
Freescale Semiconductor130
8
(Jun-2011)
Removed spec 3 from Table 27 “PFCPR1 Settings vs Frequency of Operation”
Updated spec 2a (Untrimmed VRC 1.2V) in Table 11 “PMC Electrical Specifications“ to a max value of
VDD12OUT + 17%.
Updated item 26 (Operating Current VDDA Supply) in table 14 “Electrical Specifications” from 30 mA to 40 mA.
Updated Note 11 for Table 14 (Electrical Specifications) to read IOH_F = {16,32,47,77} mA and
IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V.
Updated ID 9 in Table 11 (PMC Electrical Specifications) to
V
REG =
4.5 V, max DC output current with a max of 80 mA
V
REG
= 4.25 V, max DC output current, crank condition with a max of 40 mA
Updated Table 17 (DSPI LVDS Pad Specification) with the following:
• Spec 1 typical value updated from 40 MHz to 50 MHz
• Spec 2 added SRC conditions and associated values:
– SRC=0b00 or SRC=0b11 Min 150 mV Max 400 mV
– SRC=0b01 Min 90 mV Max 320 mV
– SRC=0b10 Min 160 mV Max 480 mV
• Spec 3
- Min value from 1.075 V to 1.06 V
- Max value from 1.325 V to 1.39 V
• Added Spec 5, 6 and 7
Updated table 17 "DSPI LVDS pad specification" to include Temperature with a min value of -40 C and max of
150 C
Updated Spec 5 of Table 18, "FMPLL Electrical Specifications" to < 400 us as the Max vaule.
Added the sentence "Violating the VCO min/max range may prevent the system from exiting reset." to the end
of Footnote 16 of Table 18, "FMPLL Electrical Specifications"
Updated Spec 1 of Table 18, "FMPLL Electrical Specifications", Crystal Reference (PLLCFG2 = 0b1) minimum
value from 40 MHz to 16 MHz.
Updated Spec 1 of Table 18, "FMPLL Electrical Specifications", External Reference (PLLCFG2 = 0b1) minimum
value from 40 MHz to 16 MHz.
Removed Note 9, 'Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1', from Table 18,
"FMPLL Electrical Specifications".
Updated ID 16 in Table 11, “PMC Electrical Specifications”, SMPS regulator clock frequency (after reset) 2.4MHz
Max
Updated Table 16 “Flash EEPROM Module Life”, spec 3, ‘Blocks with 10,001–100,000 P/E cycles’ to 5 Years.
Added Typ column to Table 25, “Flash Program and Erase Specifications”
Table 46. Revision History (continued)
Revision
(Date)
Description of changes