Datasheet

MPC5674F Microcontroller Data Sheet, Rev. 9
Electrical Characteristics
Freescale Semiconductor26
NOTE
In the following table, "untrimmed” means “at reset" and "trimmed” means “after reset".
Table 10. PMC Operating conditions
Name Parameter Condition Min Typ Max Unit Note
V
DDREG
Supply voltage VDDREG
5V nominal
LDO5V / SMPS5V mode 4.5 5 5.5 V
1
1
Voltage should be higher than maximum V
LVDREG
to avoid LVD event
V
DDREG
Supply voltage VDDREG
3V nominal
LDO3V mode 3.0 3.3 3.6 V
1
V
DD33
Supply voltage VDDSYN /
V
DD33
3.3V nominal
LDO3V mode 3.0 3.3 3.6 V
2
2
Applies to both V
DD33
(flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum V
LVD33
to avoid LVD event
V
DD
Core supply voltage — 1.14 1.2 1.32 V
3
3
Voltage should be higher than maximum V
LVD12
to avoid LVD event
Table 11. PMC Electrical Specifications
ID Name Parameter Min Typ Max Unit
1V
BG
Nominal bandgap reference voltage 0.608 0.620 0.632 V
1a — Untrimmed bandgap reference voltage V
BG
– 5% V
BG
V
BG
+ 5% V
2V
DD12OUT
Nominal VRC regulated 1.2V output VDD — 1.27 — V
2a — Untrimmed VRC 1.2V output variation before band
gap trim (unloaded)
Note: Voltage should be higher than maximum
V
LVD12
to avoid LVD event
V
DD12OUT
– 14% V
DD12OUT
V
DD12OUT
+10% V
2b — Trimmed VRC 1.2V output variation after band gap
trim (REGCTL load max. 20mA, VDD load max.
1A)
1
V
DD12OUT
– 10% V
DD12OUT
V
DD12OUT
+ 5% V
2c V
STEPV12
Trimming step V
DD12OUT
—10—mV
3V
PORC
POR rising VDD 1.2V — 0.7 — V
3a — POR VDD 1.2V variation V
PORC
– 30% V
PORC
V
PORC
+ 30%
3b — POR 1.2V hysteresis — 75 — mV
4V
LVD12
Nominal rising LVD 1.2V
Note: ~V
DD12OUT
× 0.87
—1.100— V
4a — Untrimmed LVD 1.2V variation before band gap trim
Note: Rising VDD
V
LVD12
– 6% V
LVD12
V
LVD12
+ 6% V
4b — Trimmed LVD 1.2V variation after band gap trim
Rising VDD
V
LVD12
– 3% V
LVD12
V
LVD12
+ 3% V