Datasheet

Electrical Characteristics
MPC5674F Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 29
4.6 Power Up/Down Sequencing
There is no power sequencing required among power sources during power up and power down in order to operate within
specification as long as the following two rules are met:
• When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.
• When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the
internal 3.3V regulator.
The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up
each V
DDE
/V
DDEH
first and then power up V
DD
. For power down, drop V
DD
to 0 V first, and then drop all V
DDE
/V
DDEH
supplies. There is no limit on the fall time for the power supplies.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to Table 12 and Table 13.
4.6.1 Power-Up
If V
DDE
/V
DDEH
is powered up first, then a threshold detector tristates all drivers connected to V
DDE
/V
DDEH
. There is no limit
to how long after V
DDE
/V
DDEH
powers up before V
DD
must power up. If there are multiple V
DDE
/V
DDEH
supplies, they can
be powered up in any order. For each V
DDE
/V
DDEH
supply not powered up, the drivers in that V
DDE
/V
DDEH
segment exhibit
the characteristics described in the next paragraph.
Table 12. Power Sequence Pin States for MH and AE pads
VDD VDD33 VDDE MH Pad MH+LVDS Pads
1
1
MH+LVDS pads are output-only.
AE/up-down Pads
High High High Normal operation Normal operation Normal operation
— Low High Pin is tri-stated (output buffer,
input buffer, and weak pulls
disabled)
Outputs disabled Pull-ups enabled,
pull-downs disabled
Low High Low Output low,
pin unpowered
Outputs disabled Output low,
pin unpowered
Low High High Pin is tri-stated (output buffer,
input buffer, and weak pulls
disabled)
Outputs disabled Pull-ups enabled,
pull-downs disabled
Table 13. Power Sequence Pin States for F and FS pads
VDD VDD33 VDDE F and FS pads
low low high Outputs Disabled
low high — Outputs Disabled
high low low Outputs Disabled
high low high Outputs Disabled
high high low Normal operation - except no drive current
and input buffer output is unknown.
1
1
The pad pre-drive circuitry will function normally but since VDDE is unpowered
the outputs will not drive high even though the output pmos can be enabled.
high high high Normal Operation