Datasheet

Electrical Characteristics
MPC5674F Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 35
4.7.2 LVDS Pad Specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI
module.
4.8 Oscillator and FMPLL Electrical Characteristics
Table 16. DSPI LVDS pad specification
# Characteristic Symbol Condition
Min.
Value
Typ.
Value
Max.
Value
Unit
Data Rate
1 Data Frequency f
LVDSCLK
——50—MHz
Driver Specs
2 Differential output voltage V
OD
SRC=0b00 or 0b11 150 — 400 mV
SRC=0b01 90 — 320
SRC=0b10 160 — 480
3 Common mode voltage (LVDS),
VOS
V
OS
— 1.06 1.2 1.39 V
4 Rise/Fall time T
R
/T
F
——2—ns
5 Propagation delay (Low to High) T
PLH
——4—ns
6 Propagation delay (High to Low) T
PHL
——4—ns
7 Delay (H/L), sync Mode t
PDSYNC
——4—ns
8 Delay, Z to Normal (High/Low) T
DZ
——500—ns
9 Diff Skew Itphla-tplhbI or
Itplhb-tphlaI
T
SKEW
———0.5ns
Termination
10 Trans. Line (differential Zo) — — 95 100 105 ohms
11 Temperature — — –40 — 150 C
Table 17. FMPLL Electrical Specifications
1
(V
DDSYN
= 3.0 V to 3.6 V, V
SS
=V
SSSYN
=0V, T
A
=T
L
to T
H
)
Spec Characteristic Symbol Min Max Unit
1 PLL Reference Frequency Range
2
(Normal Mode)
Crystal Reference (PLLCFG2 = 0b0)
Crystal Reference (PLLCFG2 = 0b1)
External Reference (PLLCFG2 = 0b0)
External Reference (PLLCFG2 = 0b1)
f
ref_crystal
f
ref_crystal
f
ref_ext
f
ref_ext
8
16
8
16
20
40
3
20
40
MHz
2 Loss of Reference Frequency
4
f
LOR
100 1000 kHz
3 Self Clocked Mode Frequency
5
f
SCM
416MHz
4 PLL Lock Time
6
t
LPLL
— < 400 s