Datasheet

MPC5674F Microcontroller Data Sheet, Rev. 9
Electrical Characteristics
Freescale Semiconductor36
5 Duty Cycle of Reference
7
t
DC
40 60 %
6 Frequency un-LOCK Range f
UL
–4.0 4.0 % f
sys
7 Frequency LOCK Range f
LCK
–2.0 2.0 % f
sys
8 D_CLKOUT Period Jitter
8, 9
Measured at f
SYS
Max
Cycle-to-cycle Jitter
C
Jitter
–5 5 %f
clkout
9 Peak-to-Peak Frequency Modulation Range Limit
10,11
(f
sys
Max must not be exceeded)
C
mod
04%f
sys
10 FM Depth Tolerance
12
C
mod_err
–0.25 0.25 %f
sys
11 VCO Frequency f
VCO
192 600 MHz
12 Modulation Rate Limits
13
f
mod
0.400 1 MHz
13 Predivider output frequency range
14
f
prediv
410MHz
1
All values given are initial design targets and subject to change.
2
Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default
PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.
3
Upper tolerance of less than 1% is allowed on 40MHz crystal.
4
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
5
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f
LOR
. This
frequency is measured at D_CLKOUT. A default RFD value of (0x05) is used in SCM mode, and the programmed MFD and
RFD values have no effect
6
This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
7
For Flexray operation, duty cycle requirements are higher.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
DDSYN
and V
SSSYN
and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval. D_CLKOUT divider set to divide-by-2.
9
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
jitter
+C
mod
.
10
Modulation depth selected must not result in f
pll
value greater than the f
pll
maximum specified value.
11
Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in
control register are: 2%, 3%, and 4% peak-to-peak.
12
Depth tolerance is the programmed modulation depth ±0.25% of F
sys
. Violating the VCO min/max range may prevent the
system from exiting reset.
13
Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz
will result in reduced calibration accuracy.
14
Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.
Table 17. FMPLL Electrical Specifications
1
(continued)
(V
DDSYN
= 3.0 V to 3.6 V, V
SS
=V
SSSYN
=0V, T
A
=T
L
to T
H
)
Spec Characteristic Symbol Min Max Unit