Datasheet

Electrical Characteristics
MPC5674F Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor 37
4.9 eQADC Electrical Characteristics
Table 18. Oscillator Electrical Specifications
1
(V
DDSYN
= 3.0 V to 3.6 V, V
SS
=V
SSSYN
=0V, T
A
=T
L
to T
H
)
1
All values given are initial design targets and subject to change.
Spec Characteristic Symbol Min Max Unit
1 Crystal Mode Differential Amplitude
2
(Min differential voltage between EXTAL and XTAL)
2
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode.
In that case, V
extal
–V
xtal
 400 mV criterion has to be met for oscillator’s comparator to produce output clock.
V
crystal_diff_amp
| V
extal
– V
xtal
| > 0.4 V
—V
2 Crystal Mode: Internal Differential Amplifier Noise
Rejection
V
crystal_diff_amp_nr
— | V
extal
– V
xtal
| < 0.2 V V
3 EXTAL Input High Voltage
Bypass mode, External Reference
V
IHEXT
((V
DD33
/2) + 0.4 V) —V
4 EXTAL Input Low Voltage
Bypass mode, External Reference
V
ILEXT
—
(V
DD33
/2) – 0.4 V V
5XTAL Current
3
3
I
xtal
is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
I
XTAL
13mA
6 Total On-chip stray capacitance on XTAL C
S_XTAL
—
1.5 pF
7 Total On-chip stray capacitance on EXTAL C
S_EXTAL
—
1.5 pF
8 Crystal manufacturer’s recommended capacitive load C
L
See crystal spec See crystal spec pF
9 Discrete load capacitance to be connected to EXTAL C
L_EXTAL
—
(2 × C
L
–C
S_EXTAL
–C
PCB_EXTAL
4
)
4
C
PCB_EXTAL
and C
PCB_XTAL
are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
pF
10 Discrete load capacitance to be connected to XTAL C
L_XTAL
—
(2 × C
L
–C
S_XTAL
–C
PCB_XTAL
4
)
pF
Table 19. eQADC Conversion Specifications (Operating)
Spec Characteristic Symbol Min Max Unit
1 ADC Clock (ADCLK) Frequency f
ADCLK
216MHz
2 Conversion Cycles
Single Ended Conversion Cycles 12 bit resolution
Single Ended Conversion Cycles 10 bit resolution
Single Ended Conversion Cycles 8 bit resolution
Note: Differential conversion (min) is one clock
cycle less than the single-ended
conversion values listed here.
CC
2+14
2+12
2+10
128 + 14
128 + 12
128 + 10
ADCLK cycles
3 Stop Mode Recovery Time
1
T
SR
10 — s
4 Resolution
2
—1.25 — mV
5 INL: 8 MHz ADC Clock
3
INL8 –4
4
4
4
LSB
5
6 INL: 16 MHz ADC Clock
3
INL16 –8
4
8
4
LSB
7 DNL: 8 MHz ADC Clock
3
DNL8 –3
4
3
4
LSB
8 DNL: 16 MHz ADC Clock
3
DNL16 –3
4
3
4
LSB