Datasheet

MPC5674F Microcontroller Data Sheet, Rev. 9
Electrical Characteristics
Freescale Semiconductor42
4.11 AC Specifications
4.11.1 Clocking
The Figure 16 shows the operating frequency domains of various blocks on MPC5674F.
Figure 16. MPC5674F Block Operating Frequency Domain Diagram
Table 27 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see
Table 28 and Table 29 for descriptions of bit settings).
Table 27. MPC5674F Operating Frequencies
1, 2
1
The values in the table are specified at:
V
DD
= 1.02 V to 1.32 V
V
DDE
= 3.0 V to 3.6 V
V
DDEH
= 4.5 V to 5.5 V
V
DD33
and V
DDSYN
= 3.0 V to 3.6 V
T
A
=T
L
to T
H
.
Mode
SIU_ECCR
[EBDF[0:1]]
3
f
sys
(core)
f
platf
(platform and all blocks
except eTPU)
f
etpu
(eTPU, eTPU RAM,
and NDEDI)
f
ebi_cal
4,5
Unit
Enhanced 01
11
264
264
132
132
132
132
66
33
MHz
Full 01
11
200
200
100
100
200
200
50
25
MHz
Legacy 01
11
132
132
132
132
132
132
66
33
MHz
PLL
CORE
PLATFORM /
eTPU /
EBI
CAL BUS
EXTAL
D_CLKOUT
f
platf
Note: t
cycsys
= 1 / f
sys
t
cyc
=1 / f
platf
2 = divide-by-2
 X = divide-by-X, depending on SIU_SYSDIV[BYPASS]
and SIU_SYSDIV[SYSCLKDIV].
BLOCKS /
(D_CLKOUT is not available
on all packages and cannot
be programmed for faster
than fsys/2.)
 2
PLLCFG[0:1]
SIU_SYSDIV[SYSCLKDIV[0:1]]
IPG DIV SEL
ETPU DIV SEL
SIU_SYSDIV[IPCLKDIV[0:1]]
f
etpu
SYSDIV
 X
FLASH
NDEDI
DIV
f
ebi_cal
SIU_SYSDIV[BYPASS]
X = 2, 4, 8, or 16
X=1
f
sys
SIU_ECCR[EBDF[0:1]]
f
periph