Datasheet

MPC5674F Microcontroller Data Sheet, Rev. 9
Electrical Characteristics
Freescale Semiconductor54
Figure 27. D_CLKOUT Timing
7 Input Signal Valid to D_CLKOUT
Posedge (Setup Time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
t
CIS
5.0/4.5 — ns Input setup time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0; 5.0ns
EBTS = 1; 4.5ns
8 D_CLKOUT Posedge to Input
Signal Invalid (Hold Time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
t
CIH
1.0 — ns
9 D_ALE Pulse Width t
APW
6.5 — ns The timing is for Asynchronous
external memory system.
10 D_ALE Negated to Address Invalid t
AAI
2.0/1.0
5
— ns The timing is for Asynchronous
external memory system.
ALE is measured at 50% of VDDE.
1
EBI timing specified at V
DD
= 1.08 V to 1.32 V, V
DDE
= 3.0 V to 3.6 V, V
DD33
and V
DDSYN
= 3.0 V to 3.6 V, T
A
=T
L
to T
H
, and
C
L
= 30 pF with DSC = 0b10.
2
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
270 MHz parts allow for 264 MHz system clock + 2% FM.
3
Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.
The maximum external bus frequency is 66 MHz.
4
Refer to Fast pad timing in Table 30 and Table 31.
5
ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0 C. 2.0 ns spec applies to
temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit.
Table 35. Bus Operation Timing
1
(continued)
Spec Characteristic Symbol
66 MHz (Ext. Bus Freq)
2 3
Unit Notes
Min Max
1
2
2
3
4
D_CLKOUT
V
DDE
/ 2
V
OL_F
V
OH_F