Datasheet

MPC5674F Microcontroller Data Sheet, Rev. 9
Electrical Characteristics
Freescale Semiconductor60
The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.
DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high
speed operation.
9 Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
8
Master (MTFE = 1, CPHA = 1)
t
SUI
20
4
6
20
—
—
—
—
ns
ns
ns
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
8
Master (MTFE = 1, CPHA = 1)
t
HI
–3
7
12
–3
—
—
—
—
ns
ns
ns
ns
11 Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t
SUO
—
—
—
—
5
25
13
5
ns
ns
ns
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t
HO
–5
2.5
3
–5
—
—
—
—
ns
ns
ns
ns
1
DSPI timing specified at V
DD
= 1.08 V to 1.32 V, V
DDEH
= 3.0 V to 5.5 V, V
DD33
and V
DDSYN
= 3.0 V to 3.6 V, and T
A
=T
L
to T
H
2
Speed is the nominal maximum frequency of platform clock (f
platf
). Max speed is the maximum speed allowed including
frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (f
sys
) + 2% FM.
3
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two devices communicating over a DSPI link.
4
The actual minimum SCK cycle time is limited by pad performance.
5
The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
6
The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
7
For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS
8
This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
Table 40. DSPI LVDS Timing
1, 2
1
These are typical values that are estimated from simulation.
2
See DSPI LVDS Pad related data in Table 16.
Characteristic Symbol Min Max Unit
LVDS Clock to Data/Chip Select Outputs t
LVDSDATA
–0.25 ×
t
SCYC
+0.25 ×
t
SCYC
ns
Table 39. DSPI Timing
1 2
(continued)
Spec Characteristic Symbol
Peripheral Bus Freq: 132 MHz
Unit
Min Max